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1.发明申请公开(公告)号：US20240386170A1
公开(公告)日：2024-11-21
申请号：US18787605
申请日：2024-07-29
Inventor： Haohua Zhou , Tze-Chiang Huang , Mei Hsu Wong
IPC: G06F30/30 , G06F30/367 , G06F30/39 , H01L23/50 , H01L23/528 , H01L23/538
Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.
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公开(公告)号：US12095711B2
公开(公告)日：2024-09-17
申请号：US18190881
申请日：2023-03-27
Inventor： Huan-Neng Chen , William Wu Shen , Chewn-Pu Jou , Feng Wei Kuo , Lan-Chou Cho , Tze-Chiang Huang , Jack Liu , Yun-Han Lee
CPC classification number: H04L5/14 , H04W52/0261 , Y02D30/70
Abstract: An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.
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公开(公告)号：US12038463B2
公开(公告)日：2024-07-16
申请号：US18359928
申请日：2023-07-27
Inventor： Haohua Zhou , Mei Hsu Wong , Tze-Chiang Huang
IPC: G01R27/16 , G01R31/30 , G01R31/319
CPC classification number: G01R27/16 , G01R31/30 , G01R31/31905
Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.
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公开(公告)号：US20230260970A1
公开(公告)日：2023-08-17
申请号：US18301817
申请日：2023-04-17
Inventor： Tze-Chiang Huang , King-Ho Tam , Yu-Hao Liu
IPC: H01L25/065 , H01L23/528 , H01L25/00
CPC classification number: H01L25/0657 , H01L23/5286 , H01L25/50 , H01L2225/06544 , H01L2225/06513
Abstract: Disclosed herein are related to an integrated circuit including multiple dies stacked along a direction. In one aspect, the integrated circuit includes a first die, a second die, and a third die stacked along the direction. In one aspect, the first die includes a first interface circuit to generate a signal. In one aspect, the second die includes a second interface circuit to receive the signal from the first interface circuit and generate a replicate signal of the signal. In one aspect, the third die includes a third interface circuit to receive the replicate signal from the second interface circuit.
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公开(公告)号：US20210373057A1
公开(公告)日：2021-12-02
申请号：US17236010
申请日：2021-04-21
Inventor： Haohua Zhou , Mei Hsu Wong , Tze-Chiang Huang
IPC: G01R27/16 , G01R31/30 , G01R31/319
Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.
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Patent Agency Ranking
公开(公告)号：US20230366917A1
公开(公告)日：2023-11-16
申请号：US18359928
申请日：2023-07-27
Inventor： Haohua Zhou , Mei Hsu Wong , Tze-Chiang Huang
IPC: G01R27/16 , G01R31/30 , G01R31/319
CPC classification number: G01R27/16 , G01R31/30 , G01R31/31905
Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.
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7.发明申请公开(公告)号：US20220059501A1
公开(公告)日：2022-02-24
申请号：US17037753
申请日：2020-09-30
Inventor： Igor Elkanovich , Amnon Parnass , Pei Yu , Li-Ken Yeh , Yung-Sheng Fang , Sheng-Wei Lin , Tze-Chiang Huang , King Ho Tam , Ching-Fang Chen
IPC: H01L25/065 , H04L29/06 , H04L12/66 , G06F13/40
Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.
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8.发明申请公开(公告)号：US20200175129A1
公开(公告)日：2020-06-04
申请号：US16599823
申请日：2019-10-11
Inventor： Haohua Zhou , Tze-Chiang Huang , Mei Hsu Wong
IPC: G06F17/50 , H01L23/50 , H01L23/528 , H01L23/538
Abstract: A System On Chip (SOC) current profile model for Integrated Voltage Regulator (IVR) co-design may be provided. A first current profile model may be extracted corresponding to an SOC at a first design stage of the SOC. Then it may be determined that an IVR and the SOC pass a first co-simulation based on the extracted first current profile model. Next, a second current profile model may be extracted corresponding to the SOC at a second design stage of the SOC. Then it may be determined that the IVR and the SOC pass a second co-simulation based on the extracted second current profile model. A third current profile model may be extracted corresponding to the SOC at a third design stage of the SOC. Then it may be determined that the IVR and the SOC pass a third co-simulation based on the extracted third current profile model.
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9.发明授权公开(公告)号：US10108764B2
公开(公告)日：2018-10-23
申请号：US15099941
申请日：2016-04-15
Inventor： Shereef Shehata , Sandeep Kumar Goel , Tze-Chiang Huang , Yun-Han Lee , Mei Wong
IPC: G06F17/50
Abstract: A method of estimating power consumption for a system on chip (SOC) includes simulating operation of a first sub-block to obtain power consumption information for the first sub-block including first activation information for a first IP block. The method further includes simulating operation of a second sub-block to obtain power consumption information for the second sub-block including second activation information for the first IP block and activation information for a plurality of second IP blocks. The method further includes determining a weighting factor for the first activation information for the first IP block, the second activation information for the first IP block and the activation information for each second IP block. The method further includes estimating power consumption for the SOC based on the first and second activation information for the first IP block, the activation information for at least one second IP block, and corresponding weighting factors.
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公开(公告)号：US10101796B2
公开(公告)日：2018-10-16
申请号：US15167243
申请日：2016-05-27
Inventor： Kai-Yuan Ting , Sandeep Kumar Goel , Tze-Chiang Huang , Yun-Han Lee
Abstract: A method of estimating power consumption of a processor includes accessing an electronic system level (ESL) model of the processor, the ESL model including a plurality of functional blocks, identifying a plurality of processor events by tracing activity of the plurality of functional blocks for a plurality of machine code instructions, and calculating a first power consumption value based on the plurality of processor events. The method also includes identifying a plurality of cycles by analyzing a plurality of micro-code operation codes corresponding to the plurality of machine code instructions, calculating a second power consumption value based on the plurality of cycles, and calculating a total power consumption value from the first power consumption value summed with the second power consumption value.
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