公开(公告)号：US20190245058A1

公开(公告)日：2019-08-08

申请号：US16384234

申请日：2019-04-15

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Gengming TAO ,  Xia LI

IPC: H01L29/66 ,  H01L29/737 ,  H01L23/367 ,  H01L23/495

CPC classification number: H01L29/66318 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/49568 ,  H01L29/0821 ,  H01L29/205 ,  H01L29/225 ,  H01L29/41708 ,  H01L29/7371

Abstract: A heterojunction bipolar transistor may include an emitter, a base contacting the emitter, a collector contacting the base, a sub-collector contacting the collector, and an electrical isolation layer contacting the sub-collector. The heterojunction bipolar transistor may also include a backside heatsink thermally coupled to the sub-collector and the collector. The backside heatsink may be aligned with a central axis of the emitter and the base.

公开(公告)号：US20190051750A1

公开(公告)日：2019-02-14

申请号：US15676494

申请日：2017-08-14

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Gengming TAO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L27/092 ,  H01L21/8238

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a channel disposed above the substrate, and a first dielectric layer disposed adjacent to a first side of the channel. The semiconductor device may also include a first non-insulative region disposed between the first dielectric layer and the substrate, and a second dielectric layer disposed adjacent to a second side of the channel, wherein the first dielectric layer and the second dielectric layer comprise high-k layers. In certain aspects, a second non-insulative region may be disposed above the second dielectric layer, and a third non-insulative region may be disposed adjacent to a third side of the channel.

公开(公告)号：US20180337269A1

公开(公告)日：2018-11-22

申请号：US15599157

申请日：2017-05-18

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Xia LI ,  Bin YANG

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H03F3/213 ,  H03F1/30 ,  H03F3/195 ,  G01K7/01

Abstract: A heterojunction bipolar transistor (HBT) thermal sensing device includes a well structure as a layer between an HBT sub-collector and an HBT substrate. In one instance, the HBT sub-collector contacts an emitter, a collector, and a base of the HBT thermal sensing device. The HBT thermal sensing device also includes a first side electrode in electrical contact with the quantum well structure and a second side electrode in electrical contact with the quantum well structure.

公开(公告)号：US20170062526A1

公开(公告)日：2017-03-02

申请号：US14835314

申请日：2015-08-25

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia LI ,  Seung Hyuk KANG

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1683

Abstract: A method of fabrication of a device includes forming a first electrode and a second electrode. The method further includes forming a resistive material between the first electrode and the second electrode to form a resistance-based storage element of a resistive random access memory (RRAM) device.

Abstract translation: 一种制造器件的方法包括形成第一电极和第二电极。 该方法还包括在第一电极和第二电极之间形成电阻材料以形成电阻随机存取存储器（RRAM）装置的基于电阻的存储元件。

公开(公告)号：US20160013306A1

公开(公告)日：2016-01-14

申请号：US14858992

申请日：2015-09-18

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Ming CAI

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/15 ,  H01L29/66 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/7789 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/151 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7781 ,  H01L29/7783 ,  H01L29/7785 ,  H01L29/7787 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An inner fin of a high bandgap material is on a substrate, having two vertical faces, and is surrounded by a carrier redistribution fin of a low bandgap material. The inner fin and the carrier redistribution fin have two vertical interfaces. The carrier redistribution fin has a thickness and a bandgap relative to the bandgap of the inner fin that establishes, along the two vertical interfaces, an equilibrium of a corresponding two two-dimensional electron gasses.

Abstract translation: 高带隙材料的内翅片在基板上，具有两个垂直面，并被低带隙材料的载流子再分布翅片围绕。 内鳍和载体再分布鳍具有两个垂直接口。 载流子再分布片相对于内鳍的带隙具有厚度和带隙，沿着两个垂直界面建立相应的两个二维电子气体的平衡。

公开(公告)号：US20150171314A1

公开(公告)日：2015-06-18

申请号：US14109200

申请日：2013-12-17

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Yu LU ,  Seung Hyuk KANG

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.

Abstract translation: 兼容收缩器件技术的磁阻随机存取存储器（MRAM）集成包括形成在具有一个或多个逻辑元件的公共层间金属电介质（IMD）层中的磁性隧道结（MTJ）。 MTJ连接到底部IMD层中的底部金属线和连接到顶部IMD层的顶部通孔。 MTJ基本上在配置成分离公共IMD层和底部IMD层的一个或多个底盖层之间延伸，以及被配置为分离公共IMD层和顶部IMD层的一个或多个顶盖层。 MTJ可以包括顶部电极，以连接到顶部通孔，或者通过用于较小器件技术的硬掩模直接连接到顶部通孔。 逻辑元件包括通孔，金属线和半导体器件。

公开(公告)号：US20150035039A1

公开(公告)日：2015-02-05

申请号：US14044725

申请日：2013-10-02

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Seung Hyuk KANG

IPC: H01L27/115 ,  H01L29/788

CPC classification number: H01L29/7883 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film.

Abstract translation: 一种制造多时间可编程（MTP）器件的方法包括在第二导电类型的衬底上形成第一导电类型的鳍片。 该方法还包括形成浮动栅极电介质以部分地围绕鳍片。 该方法还包括在浮栅电介质上形成浮栅。 该方法还包括在浮栅上形成耦合膜并在耦合膜上形成耦合栅极。

公开(公告)号：US20150001631A1

公开(公告)日：2015-01-01

申请号：US14109203

申请日：2013-12-17

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Ming CAI ,  Samit SENGUPTA ,  PR CHIDAMBARAM

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092

Abstract: Complementary metal oxide semiconductor (CMOS) devices include input/output (I/O) devices and core function devices. A method includes forming first conduction type wells for the I/O devices and the core function devices with a well mask. Such a method also includes creating at least one baseline device of a first conduction type, at least one first threshold voltage device of the first conduction type, and at least one second threshold device of the first conduction type by tuning a conduction type drive current ratio with a threshold voltage mask. The method also includes controlling a gate critical dimension for the first conduction type devices and/or at least one second conduction type device using a gate mask.

Abstract translation: 互补金属氧化物半导体（CMOS）器件包括输入/​​输出（I / O）器件和核心功能器件。 一种方法包括用于具有良好掩模的I / O设备和核心功能设备的第一导电型阱。 这种方法还包括通过调谐传导类型的驱动电流比率来产生第一导电类型的至少一个基线装置，第一导电类型的至少一个第一阈值电压装置和第一导电类型的至少一个第二阈值装置 具有阈值电压掩模。 该方法还包括使用栅极掩模来控制第一导电类型器件和/或至少一个第二导电型器件的栅极临界尺寸。

公开(公告)号：US20250107200A1

公开(公告)日：2025-03-27

申请号：US18473803

申请日：2023-09-25

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Biswa Ranjan PANDA

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/78

Abstract: An electronic device having one or more non-planar transistors is disclosed. At least one of the non-planar transistors comprises: one or more gate structures; and one or more gate spacers associated with each of the one or more gate structures, at least one gate spacer of the one or more gate spacers having a multi-layer dielectric structure comprising an interior wall disposed next to a respective gate structure of the one or more gate structures, wherein the interior wall is formed from a first dielectric material, an exterior wall spaced apart from the interior wall, wherein the exterior wall is formed from a second dielectric material, and a third dielectric material disposed between the interior wall and the exterior wall, wherein a dielectric constant of the third dielectric material is lower than both the dielectric constants of the first and second dielectric materials.

公开(公告)号：US20240321849A1

公开(公告)日：2024-09-26

申请号：US18340733

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Aniket PATIL ,  Dongming HE

IPC: H01L25/16 ,  G02B6/42 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/167 ,  G02B6/4251 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/16 ,  H10B80/00 ,  H01L2224/16227

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.