公开(公告)号：US20240321849A1

公开(公告)日：2024-09-26

申请号：US18340733

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Aniket PATIL ,  Dongming HE

IPC: H01L25/16 ,  G02B6/42 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/167 ,  G02B6/4251 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/16 ,  H10B80/00 ,  H01L2224/16227

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

公开(公告)号：US20210118834A1

公开(公告)日：2021-04-22

申请号：US17071432

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  John HOLMES ,  Xuefeng ZHANG ,  Dongming HE

IPC: H01L23/00

Abstract: Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

公开(公告)号：US20240421128A1

公开(公告)日：2024-12-19

申请号：US18335532

申请日：2023-06-15

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Yi-Hang LIN ,  Dongming HE ,  Lily ZHAO ,  Ryan LANE

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L27/02

Abstract: Disclosed is a semiconductor device. In an aspect, a semiconductor device includes: a first-tier passive device including a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and one or more second-tier passive devices disposed over the first-tier passive device. Each one of the one or more second-tier passive devices includes: a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and a set of through substrate vias (TSVs) passing through a corresponding substrate portion and electrically coupled to a corresponding metallization portion. The semiconductor device comprises a passive component including the passive device portion of the first-tier passive device electrically coupled to one or more passive device portions of the one or more second-tier passive devices through the metallization portions of the first-tier passive device and the one or more second-tier passive devices.

公开(公告)号：US20240319455A1

公开(公告)日：2024-09-26

申请号：US18607170

申请日：2024-03-15

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Aniket PATIL ,  Dongming HE

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: G02B6/4245 ,  G02B6/4248 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16155 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2924/1427 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

公开(公告)号：US20220270995A1

公开(公告)日：2022-08-25

申请号：US17185244

申请日：2021-02-25

Applicant: QUALCOMM Incorporated

Inventor： Wei HU ,  Dongming HE ,  Wen YIN ,  Zhe GUAN ,  Lily ZHAO

IPC: H01L23/00

Abstract: Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar such that during solder reflow, solder wetting of sidewall of the pillar is minimized or prevented all together. The die interconnect may also include a low wetting layer formed on the wetting barrier, which can further mitigate solder wetting problems.

公开(公告)号：US20240006361A1

公开(公告)日：2024-01-04

申请号：US17855189

申请日：2022-06-30

Applicant: QUALCOMM Incorporated

Inventor： Wei WANG ,  Dongming HE ,  Yangyang SUN ,  Wei HU

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/05 ,  H01L24/04 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/1146 ,  H01L2224/11903 ,  H01L24/81 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81815

Abstract: An integrated device comprising a die portion that includes a plurality of pads and a plurality of under bump metallization interconnects coupled to the plurality of pads, where the plurality of under bump metallization interconnects comprises a first under bump metallization interconnect. The integrated device includes a plurality of pillar interconnects coupled to the plurality of under bump metallization interconnects, where the plurality of pillar interconnects includes a first pillar interconnect. The first pillar interconnect includes a first width that corresponds to a widest part of the first pillar interconnect, and a second width that corresponds to a part of the first pillar interconnect that is vertically farthest away from the first under bump metallization interconnect, wherein the second width is less than the first width.

公开(公告)号：US20230384367A1

公开(公告)日：2023-11-30

申请号：US17804658

申请日：2022-05-31

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Amer Christophe Gaetan CASSIER ,  Stanley Seungchul SONG ,  Lily ZHAO ,  Dongming HE

IPC: G01R31/28 ,  H01L23/00

CPC classification number: G01R31/2884 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2924/1431 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14515 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/11916 ,  H01L2224/11903 ,  H01L2224/0401 ,  H01L2224/05573 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05147 ,  H01L2224/05124 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/13147 ,  H01L2224/13005 ,  H01L2224/13016

Abstract: Disclosed are integrated circuit structures with interconnects of small size, also referred to micro-bumps. As pitches of micro-bumps become smaller, their sizes also become small. This makes it difficult to probe the integrated circuit structure to verify their operations. To enable probing, test pads of larger pitches are provided. The test pads, usually formed of metal, may be protected with solder caps.

公开(公告)号：US20230223375A1

公开(公告)日：2023-07-13

申请号：US17574360

申请日：2022-01-12

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Dongming HE ,  Lily ZHAO

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/73 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/26 ,  H01L25/50 ,  H01L24/92 ,  H01L2225/06541 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06565 ,  H01L24/30 ,  H01L2224/301 ,  H01L24/33 ,  H01L2224/33181 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L24/16 ,  H01L2224/16148 ,  H01L24/13 ,  H01L2224/13082 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L24/06 ,  H01L2224/06181 ,  H01L24/05 ,  H01L2224/0557 ,  H01L2224/26125 ,  H01L2224/9211

Abstract: A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

公开(公告)号：US20210407939A1

公开(公告)日：2021-12-30

申请号：US16917295

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Yangyang SUN ,  Dongming HE ,  Lily ZHAO

IPC: H01L23/00

Abstract: Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

公开(公告)号：US20240413112A1

公开(公告)日：2024-12-12

申请号：US18330657

申请日：2023-06-07

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Hung-Yuan HSU ,  Yujen CHEN

IPC: H01L23/00

Abstract: An integrated device includes a die having a contact pad and a solder cap electrically connected to the contact pad by a multi-layer interconnect pillar. The multi-layer interconnect pillar includes a base reinforcement layer, a cap reinforcement layer, and one or more solder layers disposed between the base reinforcement layer and the cap reinforcement layer.