公开(公告)号：US20220270995A1

公开(公告)日：2022-08-25

申请号：US17185244

申请日：2021-02-25

Applicant: QUALCOMM Incorporated

Inventor： Wei HU ,  Dongming HE ,  Wen YIN ,  Zhe GUAN ,  Lily ZHAO

IPC: H01L23/00

Abstract: Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar such that during solder reflow, solder wetting of sidewall of the pillar is minimized or prevented all together. The die interconnect may also include a low wetting layer formed on the wetting barrier, which can further mitigate solder wetting problems.