公开(公告)号：US20240290845A1

公开(公告)日：2024-08-29

申请号：US18660198

申请日：2024-05-09

申请人： FUJI ELECTRIC CO., LTD.

发明人： Yasunori AGATA ,  Takashi YOSHIMURA ,  Hiroshi TAKISHITA

IPC分类号： H01L29/36 ,  H01L21/265 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/868

CPC分类号： H01L29/36 ,  H01L21/265 ,  H01L27/0716 ,  H01L29/1095 ,  H01L29/739 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/868 ,  H01L29/0611

摘要： Provided is a semiconductor device including a buffer region. Provided is a semiconductor device including: semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type provided in the semiconductor substrate; and a buffer region of the first conductivity type provided in the drift layer, the buffer region having a plurality of peaks of a doping concentration, wherein the buffer region has: a first peak which has a predetermined doping concentration, and is provided the closest to a back surface of the semiconductor substrate among the plurality of peaks; and a high-concentration peak which has a higher doping concentration than the first peak, and is provided closer to an upper surface of the semiconductor substrate than the first peak is.

公开(公告)号：US20240290828A1

公开(公告)日：2024-08-29

申请号：US18426051

申请日：2024-01-29

申请人： Littelfuse Semiconductor (Wuxi) Co., Ltd.

发明人： Xingchong Gu ,  Jifeng Zhou

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/0619 ,  H01L29/0834 ,  H01L29/1012 ,  H01L29/66363

摘要： Techniques for reducing peak on-state voltage of a semiconductor device fabricated in a wafer. A substrate layer is provided. An isolation structure is provided to laterally isolate the semiconductor device from other semiconductor devices in the wafer. A tub structure is formed in the substrate layer. A base layer is provided such that the base layer is disposed under the substrate layer. The base layer includes an anode having an associated active region that includes a drift region in the substrate layer. The tub structure is disposed inside the active region such that presence of the tub structure reduces a thickness of the drift region.

公开(公告)号：US12074200B2

公开(公告)日：2024-08-27

申请号：US18370626

申请日：2023-09-20

申请人： FUJI ELECTRIC CO., LTD.

发明人： Keiji Okumura

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/745 ,  H01L21/04 ,  H01L29/04 ,  H01L29/06

CPC分类号： H01L29/1095 ,  H01L29/083 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/417 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/745 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L21/0465 ,  H01L21/047 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0696

摘要： An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

公开(公告)号：US20240282856A1

公开(公告)日：2024-08-22

申请号：US18648180

申请日：2024-04-26

申请人： Micron Technology, Inc.

发明人： Yoshitaka Nakamura ,  Yi Fang Lee ,  Jerome A. Imonigie ,  Scott E. Sills ,  Aaron Michael Lowe

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/417 ,  H01L29/45 ,  H10B12/00

CPC分类号： H01L29/7827 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/41741 ,  H01L29/45 ,  H10B12/05 ,  H10B12/31

摘要： Some embodiments include an integrated assembly having an access device between a storage element and a conductive structure. The access device has channel material which includes semiconductor material. The channel material has a first end and an opposing second end, and has a side extending from the first end to the second end. The first end is adjacent the conductive structure, and the second end is adjacent the storage element. Conductive gate material is adjacent the side of the channel material. A first domed metal-containing cap is over the conductive structure and under the channel material and/or a second domed metal-containing cap is over the channel material and under the storage element. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240282842A1

公开(公告)日：2024-08-22

申请号：US18636401

申请日：2024-04-16

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC分类号： H01L29/66 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532

摘要： According to another embodiment, a method of forming a transistor is provided. The method includes the following operations: providing a substrate; providing a source over the substrate; providing a channel connected to the source; providing a drain connected to the channel; providing a gate insulator adjacent to the channel; providing a gate adjacent to the gate insulator; providing a first interlayer dielectric between the source and the gate; and providing a second interlayer dielectric between the drain and the gate, wherein at least one of the formation of the source, the drain, and the channel includes about 20-95 atomic percent of Sn.

公开(公告)号：US12068406B2

公开(公告)日：2024-08-20

申请号：US17248989

申请日：2021-02-16

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Peter Coppens ,  Peter Moens ,  Joris Baele

IPC分类号： H01L29/778 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/2003

摘要： A High Electron Mobility Transistor (HEMT) includes a source, a drain, a channel layer extending between the source and the drain, a barrier layer formed in contact with the channel layer, and extending between the source and the drain, and a gate formed in contact with, and covering at least a portion of, the barrier layer. The gate has gate edge portions and a gate central portion, and dielectric spacers may be formed over the gate edge portions, with the dielectric spacers having a first width therebetween proximal to the gate, and a second width therebetween distal from the gate, where the second width is longer than the first width.

公开(公告)号：US12068400B2

公开(公告)日：2024-08-20

申请号：US17737003

申请日：2022-05-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chun-Tsung Kuo ,  Chuan-Feng Chen

IPC分类号： H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/732 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272

摘要： A BJT and methods of forming the same are described. The BJT includes a collector region disposed in a substrate, a lower base structure disposed on the collector region, a first dielectric layer surrounding a bottom portion of the lower base structure, and a second dielectric layer surrounding a top portion of the lower base structure. The first dielectric layer includes a first oxide, the second dielectric layer includes a second oxide, and the first and second oxides have different densities. The BJT further includes an upper base structure disposed on the second dielectric layer and the lower base structure, an emitter region disposed on the lower base structure, a sidewall spacer structure disposed between the emitter region and the upper base structure, and the sidewall spacer structure includes a material different from materials of the first and second dielectric layers.

公开(公告)号：US12068319B2

公开(公告)日：2024-08-20

申请号：US16141000

申请日：2018-09-25

申请人： INTEL CORPORATION

发明人： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani ,  Abhishek A. Sharma

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L29/10 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L27/092 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28194 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66537 ,  H01L29/6659

摘要： Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

公开(公告)号：US20240274716A1

公开(公告)日：2024-08-15

申请号：US18324238

申请日：2023-05-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hsin Fu Lin ,  Shiang-Hung Huang ,  Pei-Shan Hsieh

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/26506 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/1041 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/66803

摘要： A field effect transistor includes a source-side doped well, a drift-region well, a source region, a drain region; a shallow trench isolation structure including a first portion overlying the drift-region well and laterally spaced from the source-side doped well; a gate dielectric layer; a gate electrode overlying the gate dielectric layer; and a proximal doped layer stack embedded within the drift-region well and interposed between the source-side doped well and the first portion of the shallow trench isolation structure. Proximal doped semiconductor layers of the proximal doped layer stack have different average atomic concentrations of dopants of the second conductivity type.

公开(公告)号：US20240274698A1

公开(公告)日：2024-08-15

申请号：US18583764

申请日：2024-02-21

申请人： FUJI ELECTRIC CO., LTD.

发明人： Misaki UCHIDA ,  Takashi YOSHIMURA ,  Shuntaro YAGUCHI

IPC分类号： H01L29/739 ,  H01L27/07 ,  H01L29/10 ,  H01L29/32 ,  H01L29/36 ,  H01L29/861

CPC分类号： H01L29/7397 ,  H01L27/0727 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/36 ,  H01L29/861

摘要： Provided is a semiconductor device comprising: a drift region in a semiconductor substrate having a front surface and a back surface; and a buffer region in the back surface side of the semiconductor substrate relative to the drift region in a depth direction of the semiconductor substrate, wherein the buffer region has a group of concentration peaks including one or more concentration peaks of a doping concentration, the group of concentration peaks includes a first concentration peak provided closest, among the one or more concentration peaks, to the back surface of the semiconductor substrate, the semiconductor substrate includes a first hydrogen peak which is a peak of an atomic density of hydrogen, provided in a same depth position as that of the first concentration peak or in the back surface side of the semiconductor substrate relative to a depth position of the first concentration peak.