公开(公告)号：US20220189974A1

公开(公告)日：2022-06-16

申请号：US17654028

申请日：2022-03-08

申请人： Micron Technology, Inc.

发明人： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC分类号： H01L27/11521 ,  H01L27/11551 ,  H01L27/11541 ,  H01L21/768 ,  H01L27/11548 ,  H01L27/11575

摘要： A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US10896912B2

公开(公告)日：2021-01-19

申请号：US16359070

申请日：2019-03-20

申请人： International Business Machines Corporation

发明人： Alexander Reznicek ,  Karthik Balakrishnan ,  Tak Ning ,  Bahman Hekmatshoartabari

IPC分类号： H01L27/11541 ,  H01L29/788 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/28

摘要： A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

公开(公告)号：US20200303388A1

公开(公告)日：2020-09-24

申请号：US16359070

申请日：2019-03-20

申请人： International Business Machines Corporation

发明人： Alexander Reznicek ,  Karthik Balakrishnan ,  Tak Ning ,  Bahman Hekmatshoartabari

IPC分类号： H01L27/11541 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/788

摘要： A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

公开(公告)号：US10559700B2

公开(公告)日：2020-02-11

申请号：US15058601

申请日：2016-03-02

申请人： JONKER LLC

发明人： David Liu

IPC分类号： H01L29/788 ,  H01L29/423 ,  H01L27/11541 ,  H01L27/11558 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11521 ,  H01L29/78

摘要： A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.

公开(公告)号：US10325918B2

公开(公告)日：2019-06-18

申请号：US15428823

申请日：2017-02-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei Cheng Wu ,  Li-Feng Teng

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L27/11531 ,  H01L29/423 ,  H01L27/11568 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11541 ,  H01L27/11543

摘要： A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US10297605B2

公开(公告)日：2019-05-21

申请号：US15913286

申请日：2018-03-06

申请人： Allegro MicroSystems, LLC

发明人： Yigong Wang

IPC分类号： H01L27/11521 ,  H01L27/11558 ,  H01L27/11541 ,  H01L27/11543

摘要： Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a single polysilicon EEPROM and a double polysilicon EEPROM. The two-in-one hybrid EEPROM can be programmed and/or erased as a single polysilicon EEPROM and/or as a double polysilicon EEPROM. The hybrid EEPROM memory cell includes a programmable capacitor disposed on a substrate. The programmable capacitor includes a floating gate forming a first polysilicon layer, an oxide-nitride-oxide (ONO) layer having disposed over a first surface of the floating gate, and a control gate forming a second polysilicon layer with the control gate formed over a first surface of the ONO layer to form a hybrid EEPROM having a single polysilicon layer and a double polysilicon EEPROM. The single polysilicon EEPROM includes the first polysilicon layer and the double polysilicon EEPROM includes the first and second polysilicon layers.

公开(公告)号：US20190067306A1

公开(公告)日：2019-02-28

申请号：US15685690

申请日：2017-08-24

申请人： Micron Technology, Inc.

发明人： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC分类号： H01L27/11521 ,  H01L27/11551 ,  H01L27/11541

摘要： A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US10127987B2

公开(公告)日：2018-11-13

申请号：US15834063

申请日：2017-12-07

申请人： eMemory Technology Inc.

发明人： Chia-Jung Hsu ,  Wein-Town Sun

IPC分类号： G11C16/04 ,  G11C16/14 ,  H03K19/088 ,  H01L27/11541 ,  G11C7/04 ,  G11C7/10 ,  G11C16/12 ,  H01L27/11558 ,  H01L29/423 ,  G11C16/26 ,  H01L27/11524 ,  G11C16/34 ,  H01L29/78 ,  H03K17/082 ,  H01L29/788

摘要： A method for operating a NVM cell is disclosed. The NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor on an N well. The floating gate transistor includes a floating gate and a floating gate extension capacitively coupled to an erase gate region. The method includes erasing the NVM cell by applying an N well voltage VNW to the N well, wherein VNW>0V; applying a source line voltage VSL to a source doping region of the select transistor, wherein VSL=0V; applying a word line voltage VWL to a select gate of the select transistor, wherein VWL=0V; applying a bit line voltage VBL to a drain doping region of the floating gate transistor, wherein VBL=0V; and applying an erase line voltage VEL to the erase gate region, wherein VEL=VEE.

公开(公告)号：US09773796B2

公开(公告)日：2017-09-26

申请号：US14640784

申请日：2015-03-06

申请人： Chang Hyun Lee ,  Jin-Kyu Kim

发明人： Chang Hyun Lee ,  Jin-Kyu Kim

IPC分类号： H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11541

CPC分类号： H01L27/11556 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11541 ,  H01L27/11573

摘要： A non-volatile memory device including a cell array area including a plurality of memory cells and word lines and bit lines, which are connected to the plurality of memory cells, a core circuit area including a page buffer circuit and a row decoder circuit, the pager buffer circuit configured to temporarily store data input to and output from the plurality of memory cells, and the row decoder circuit configured to select some of the word lines corresponding to an address input thereto, and an input/output circuit area including a data input/output buffer circuit, the data input/output buffer circuit configured to at least one of transmit data to the page buffer circuit and receive data from the page buffer circuit, and the input/output circuit area including at least one asymmetrical transistor having a source region and a drain region asymmetrically disposed with respect to the gate structure may be provided.

公开(公告)号：US09754788B2

公开(公告)日：2017-09-05

申请号：US14797478

申请日：2015-07-13

申请人： UNITED MICROELECTRONICS CORP.

发明人： Ji-Gang Pan ,  Han-Chuan Fang ,  Boon-Tiong Neo

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/321 ,  H01L27/11531 ,  H01L27/11541

CPC分类号： H01L21/28273 ,  H01L21/32056 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L27/11531 ,  H01L27/11541

摘要： A manufacturing method of a semiconductor structure having an array area and a periphery area is provided. The manufacturing method includes the following steps. A substrate is provided. A plurality of trenches is formed on the substrate. The plurality of trenches is filled with insulating material to form at least one first insulating layer. A polysilicon layer is deposited on the substrate and the first insulating layer. A photoresist mask is formed on the periphery area. A portion of the polysilicon layer on the array area is etched, such that a top surface of the polysilicon layer on the array area is higher than the first insulating layer and lower than a top surface of the polysilicon layer on the periphery area. The photoresist mask is removed. A planarization process is implemented to remove a portion of the polysilicon layer on the array area and on the periphery area.