- 专利标题： Manufacturing method of semiconductor structure including planarizing a polysilicon layer over an array area and a periphery area
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申请号： US14797478申请日： 2015-07-13
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公开(公告)号： US09754788B2公开(公告)日： 2017-09-05
- 发明人: Ji-Gang Pan , Han-Chuan Fang , Boon-Tiong Neo
- 申请人： UNITED MICROELECTRONICS CORP.
- 申请人地址： TW Hsinchu
- 专利权人： UNITED MICROELECTRONICS CORP.
- 当前专利权人： UNITED MICROELECTRONICS CORP.
- 当前专利权人地址： TW Hsinchu
- 代理机构： WPAT, PC
- 主分类号： H01L21/28
- IPC分类号： H01L21/28 ; H01L21/3205 ; H01L21/3213 ; H01L21/321 ; H01L27/11531 ; H01L27/11541
摘要：
A manufacturing method of a semiconductor structure having an array area and a periphery area is provided. The manufacturing method includes the following steps. A substrate is provided. A plurality of trenches is formed on the substrate. The plurality of trenches is filled with insulating material to form at least one first insulating layer. A polysilicon layer is deposited on the substrate and the first insulating layer. A photoresist mask is formed on the periphery area. A portion of the polysilicon layer on the array area is etched, such that a top surface of the polysilicon layer on the array area is higher than the first insulating layer and lower than a top surface of the polysilicon layer on the periphery area. The photoresist mask is removed. A planarization process is implemented to remove a portion of the polysilicon layer on the array area and on the periphery area.
公开/授权文献
- US20170018432A1 MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE 公开/授权日：2017-01-19
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