公开(公告)号：US08541262B2

公开(公告)日：2013-09-24

申请号：US12874816

申请日：2010-09-02

Applicant: Yi-Jen Lai ,  You-Hua Chou ,  Hon-Lin Huang ,  Huai-Tei Yang

Inventor： Yi-Jen Lai ,  You-Hua Chou ,  Hon-Lin Huang ,  Huai-Tei Yang

IPC: H01L23/50

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05655 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

公开(公告)号：US20130062777A1

公开(公告)日：2013-03-14

申请号：US13592540

申请日：2012-08-23

Applicant: Tamotsu OGATA

Inventor： Tamotsu OGATA

IPC: H01L23/48

CPC classification number: H01L23/522 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Also in a semiconductor integrated circuit device including a copper embedded wiring as a main wiring layer, generally, the uppermost-layer wiring layer is often an aluminum-based pad layer in order to ensure wire bonding characteristics. The aluminum-based pad layer is also generally used as a wiring layer (general intercoupling wiring such as power source wiring or signal wiring). However, such a general intercoupling wiring has a relatively large wiring length. This causes a demerit for the device to be susceptible to damages during a plasma treatment due to the antenna effect, and other demerits. With the present invention, in a semiconductor integrated circuit device including a metal multilayer wiring system having a lower-layer embedded type multilayer wiring layer and an upper-layer non-embedded type aluminum-based pad metal layer, the non-embedded type aluminum-based pad metal layer substantially does not have a power supply ring wiring.

Abstract translation: 同样在包括铜嵌入布线作为主布线层的半导体集成电路器件中，通常为了确保引线接合特性，最上层布线层通常是铝基焊盘层。 铝基焊盘层也通常用作布线层（一般的互耦合布线，例如电源布线或信号布线）。 然而，这种一般的互相布线具有相对较大的布线长度。 这导致器件在等离子体处理期间由于天线效应以及其他缺点而容易受到损坏的缺点。 通过本发明，在包括具有下层嵌入式多层布线层和上层非嵌入式铝基焊盘金属层的金属多层布线系统的半导体集成电路装置中，非嵌入式铝 - 基底垫金属层基本上不具有电源环布线。

公开(公告)号：US08288283B2

公开(公告)日：2012-10-16

申请号：US13308108

申请日：2011-11-30

Applicant: Mona M. Eissa ,  Brian E. Zinn

Inventor： Mona M. Eissa ,  Brian E. Zinn

IPC: H01L21/461 ,  H01L21/302

CPC classification number: H01L21/7684 ,  C09G1/02 ,  H01L21/3212 ,  H01L21/76877 ,  H01L23/53252 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05006 ,  H01L2224/05017 ,  H01L2224/05026 ,  H01L2224/05155 ,  H01L2224/05541 ,  H01L2224/05546 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05664 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A process of forming an integrated circuit using a palladium CMP operation in which 25 to 125 ppm aluminum is added to the CMP slurry, allowing a palladium removal rate of at least 80 nanometers per minute at a polish pad pressure less than 9 psi and a surface speed between 1.9 and 2.2 meters per second. The palladium CMP operation may be applied to form a palladium bond pad cap after which an external bond element is formed on the palladium bond pad cap. Alternatively, the palladium CMP operation may be applied to form a palladium interconnect conductor in a first dielectric layer.

Abstract translation: 使用钯CMP操作形成集成电路的过程，其中将25至125ppm的铝添加到CMP浆料中，使得在抛光垫压力小于9psi下的至少80纳米/分钟的钯去除速率和表面 速度介于1.9到2.2米/秒之间。 可以施加钯CMP操作以形成钯键垫帽，之后在钯键合垫帽上形成外部结合元件。 或者，可以应用钯CMP操作以在第一介电层中形成钯互连导体。

公开(公告)号：US20120104600A1

公开(公告)日：2012-05-03

申请号：US13344628

申请日：2012-01-06

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

IPC: H01L23/485

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/10122 ,  H01L2224/10126 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2224/05552

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.

Abstract translation: 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括在设计敏感结构和钝化层之间形成的电介质材料。 该设计敏感结构包括通过通孔连接器电连接和机械地连接到更高布线层的下布线层。 还提供了一种方法和结构。

公开(公告)号：US20120094469A1

公开(公告)日：2012-04-19

申请号：US13219099

申请日：2011-08-26

Applicant: Didier Landru

Inventor： Didier Landru

IPC: H01L21/30 ,  H01L21/28

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0332 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05006 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05576 ,  H01L2224/05578 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/04941 ,  H01L2924/00

Abstract: The present invention relates to a process for realizing a connecting structure in a semiconductor substrate, and the semiconductor substrate realized accordingly. The semi-conductor substrate has at least a first surface, and is foreseen for a 3D integration with a second substrate along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value. This process includes growing a diffusion barrier structure for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, wherein a first end surface, being the most outward surface of the diffusion barrier structure and being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure can have a length, in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length of the diffusion barrier structure is chosen such that in a 3D integrated structure a diffusion of elements out of a conductive layer of the second substrate is prevented in the integrated state.

Abstract translation: 本发明涉及实现半导体衬底中的连接结构的方法，并且相应地实现了半导体衬底。 半导体衬底具有至少第一表面，并且预期用于沿着第一表面与第二衬底的3D集成，其中3D积分在具有不对准值的至少一个维度中受到横向错位。 该方法包括生长扩散阻挡结构，用于防止元件从导电层扩散到半导体衬底的其余部分中，其中第一端面是扩散阻挡结构的最外表面，并且基本平行于第一表面 沿垂直于第一表面的方向并且从衬底朝着第一表面延伸的扩散阻挡结构的长度可以在横向不对准的方向上具有取决于不对准值的长度，其中， 扩散阻挡结构被选择为使得在3D集成结构中，在整合状态下防止元件从第二衬底的导电层扩散。

公开(公告)号：US08114767B2

公开(公告)日：2012-02-14

申请号：US12046616

申请日：2008-03-12

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

IPC: H01L21/4763

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/10122 ,  H01L2224/10126 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2224/05552

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.

Abstract translation: 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括在设计敏感结构和钝化层之间形成的电介质材料。 该设计敏感结构包括通过通孔连接器电连接和机械地连接到更高布线层的下布线层。 还提供了一种方法和结构。

公开(公告)号：US08084858B2

公开(公告)日：2011-12-27

申请号：US12424001

申请日：2009-04-15

Applicant: Timothy H. Daubenspeck ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Steven L. Wright ,  Edmund Sprogis

Inventor： Timothy H. Daubenspeck ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Steven L. Wright ,  Edmund Sprogis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/03 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05552

Abstract: In one embodiment, a sub-pad assembly of metal structures is located directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure abutting the metal pad, a lower level metal line structure located underneath the upper level metal line structure, and a set of metal vias that provide electrical connection between the lower level metal line structure located underneath the upper level metal line structure. In another embodiment, the reliability of a C4 ball is enhanced by employing a metal pad structure having a set of integrated metal vias that are segmented and distributed to facilitate uniform current density distribution within the C4 ball. The areal density of the cross-sectional area in the plurality of metal vias is higher at the center portion of the metal pad than at the peripheral portion of the planar portion of the metal pad.

Abstract translation: 在一个实施例中，金属结构的子垫组件位于金属垫的正下方。 子焊盘组件包括邻接金属焊盘的上层金属线结构，位于上层金属线结构下方的下层金属线结构，以及一组在下层金属线结构之间提供电连接的金属通孔 在上层金属线结构下方。 在另一个实施例中，C4球的可靠性通过使用具有一组集成金属通孔的金属焊盘结构而被增强，所述集成金属通孔被分段和分配以便于在C4球内均匀的电流密度分布。 在金属焊盘的中心部分，多个金属通孔中的横截面面积的面密度高于在金属焊盘的平面部分的周边部分。

公开(公告)号：US20100301488A1

公开(公告)日：2010-12-02

申请号：US12662807

申请日：2010-05-04

Applicant: Noriaki Oda ,  Shinichi Chikaki

Inventor： Noriaki Oda ,  Shinichi Chikaki

IPC: H01L23/522

CPC classification number: H01L23/5329 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/45099

Abstract: In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure.

Abstract translation: 在半导体器件中，在平面图中，在与焊盘重叠的区域中，依次层叠下层多层互连结构，中间通孔级绝缘中间层和上层多层互连结构。 上部多层互连结构的上部互连和过孔形成为连接到焊盘放置区域中的焊盘; 中间通孔级绝缘中间层不具有将上部多层互连结构中的互连或通孔与其中形成的下部多层互连结构中的互连或通孔连接的导电材料层; 并且包含在下层多层互连结构中的通孔级绝缘夹层中的通孔占据的面积比例小于上层多层互连结构中包含的通孔级绝缘夹层中通孔占据的面积比 互连结构。

公开(公告)号：US20100267214A1

公开(公告)日：2010-10-21

申请号：US12785601

申请日：2010-05-24

Applicant: Makoto TAKAHASHI ,  Kouichi NAGAI

Inventor： Makoto TAKAHASHI ,  Kouichi NAGAI

IPC: H01L21/02

CPC classification number: H01L27/11507 ,  H01L21/7685 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/65 ,  H01L2224/02166 ,  H01L2224/03 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05546 ,  H01L2224/05556 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: According to the method for manufacturing a semiconductor device, a surface of a lower, insulating film (55) is planarized by CMP or the like, and an upper insulating film (56) and a protective metal film (59) are formed on the lower insulating film (55). Accordingly, the upper insulating film (56) and the protective metal film (59) are formed in such a manner they have an excellent coverage and the water/hydrogen blocking capability of the upper insulating film (56) and the protective metal film (59) is maximized.

Abstract translation: 根据半导体器件的制造方法，通过CMP等对下部绝缘膜（55）的表面进行平面化，在下部绝缘膜（56）和下部绝缘膜（56）上形成上部绝缘膜（56）和保护用金属膜 绝缘膜（55）。 因此，上绝缘膜56和保护金属膜59形成为具有优异的覆盖度和上绝缘膜56和保护金属膜59的水/氢阻断能力 ）最大化。

公开(公告)号：US07745255B2

公开(公告)日：2010-06-29

申请号：US12010807

申请日：2008-01-30

Applicant: Jae-Hyun Lee ,  Hyung-Moo Park

Inventor： Jae-Hyun Lee ,  Hyung-Moo Park

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/05006 ,  H01L2224/05083 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/06102 ,  H01L2224/85375 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: An electronic device having a bonding pad structure and a method of fabricating the same is provided. The electronic device may include a first bonding pads formed on the substrate. A second bonding pad may be formed on the lower insulating layer. The second bonding pads may be spaced apart from the first bonding pads. The second bonding pads may have a top surface formed at a higher level than the first bonding pads.

Abstract translation: 提供具有接合焊盘结构的电子器件及其制造方法。 电子器件可以包括形成在衬底上的第一焊盘。 第二接合焊盘可以形成在下绝缘层上。 第二接合焊盘可以与第一接合焊盘间隔开。 第二接合焊盘可以具有形成在比第一接合焊盘更高的高度的顶表面。