公开(公告)号：US20240194535A1

公开(公告)日：2024-06-13

申请号：US18080017

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Navneet Jain ,  Hongru Ren ,  Alexander Derrickson ,  Jianwei Peng ,  Bipul C. Paul

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/423 ,  H01L29/49 ,  H10B63/00

CPC classification number: H01L21/823475 ,  H01L21/76895 ,  H01L29/42316 ,  H01L29/4933 ,  H10B63/34

Abstract: Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.

公开(公告)号：US20240194528A1

公开(公告)日：2024-06-13

申请号：US18065060

申请日：2022-12-13

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kisik Choi ,  Nicolas Jean Loubet ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/76897 ,  H01L21/28141 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0694 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/78642

Abstract: A semiconductor device is provided. The semiconductor device includes source/drain (S/D) epitaxy, a gate stack adjacent to the S/D epitaxy, a semiconductor layer underlying the gate stack and including a semiconductor material surrounded by an inner spacer, an etch stop layer underlying the semiconductor layer, back trench S/D epitaxy and a self-aligned backside contact. The backside trench S/D epitaxy contacts the S/D epitaxy and is insulated from the semiconductor material by the inner spacer. The self-aligned backside contact contacts the backside trench S/D epitaxy and is insulated from the semiconductor material by the etch stop layer.

公开(公告)号：US12009426B2

公开(公告)日：2024-06-11

申请号：US17827457

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon Jhy Liaw

IPC: H01L29/94 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78 ,  H01L31/062

CPC classification number: H01L29/7848 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/66545 ,  Y02E10/50

Abstract: The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature.

公开(公告)号：US12009399B2

公开(公告)日：2024-06-11

申请号：US17222100

申请日：2021-04-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jyun Huang ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28247 ,  H01L21/31105 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/66545 ,  H01L2029/7858

Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.

公开(公告)号：US12009265B2

公开(公告)日：2024-06-11

申请号：US18068110

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/308 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

公开(公告)号：US20240178132A1

公开(公告)日：2024-05-30

申请号：US18434077

申请日：2024-02-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Zhen YU ,  Lin-Yu HUANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L23/522 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer, a second insulating layer formed over the first insulating layer, and a conductive structure formed within the second insulating layer. The conductive structure includes a metal line having a plane top surface, a bottom surface having a first concave recess portion and a plane portion, and a sidewall adjoining the plane top surface and the plane portion of the bottom surface. The conductive structure also includes a first metal feature formed within the first concave recess. The semiconductor device structure further includes a second metal feature formed below the first insulating layer and electrically connected to the first metal feature.

公开(公告)号：US20240172423A1

公开(公告)日：2024-05-23

申请号：US18419066

申请日：2024-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Heon LEE ,  Munjun KIM ,  ByeongJu BAE

IPC: H10B12/00 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/8234

CPC classification number: H10B12/482 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/823475 ,  H01L21/823481 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/485

Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

公开(公告)号：US20240162320A1

公开(公告)日：2024-05-16

申请号：US18055341

申请日：2022-11-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L29/423 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823412 ,  H01L21/823475 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/7869 ,  H01L29/78696

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit uses Cross field effect transistors (FETs) with a first device, such as n-type device, having a first channel oriented in a first direction and connected to a ground reference voltage level provided by a backside metal layer. The Cross FETs also use a second device, such as the p-type device, having a second channel oriented in a second direction orthogonal to the first direction and connected to a power supply reference voltage level provided by a frontside metal layer. A micro through silicon via (TSV) traverses the silicon substrate layer in order to be placed between the backside metal layer and the source region of an n-type device. The power connections reduce on-die area, reduces semiconductor fabrication complexity, which improves wafer yield, and reduces voltage droop, which increases performance.

公开(公告)号：US20240162151A1

公开(公告)日：2024-05-16

申请号：US18054349

申请日：2022-11-10

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Tsung-Sheng Kang ,  Koichi Motoyama ,  Oscar van der Straten

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088

Abstract: A semiconductor device includes a shallow trench isolation region extending from a first end surface to a second end surface. The semiconductor device further includes an inner layer dielectric region extending from a third end surface to a fourth end surface. The inner layer dielectric region is arranged such that the fourth end surface is in direct contact with the first end surface. The semiconductor device further includes a transistor arranged in the inner layer dielectric region and a contact via electrically connecting the transistor to a buried power rail. The contact via extends from the second end surface to the third end surface and is narrower at the fourth end surface than at the first end surface.

公开(公告)号：US20240153864A1

公开(公告)日：2024-05-09

申请号：US17980281

申请日：2022-11-03

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  Chanro Park ,  Hsueh-Chung Chen ,  Yann Mignot

IPC: H01L23/522 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/092

Abstract: A semiconductor structure includes a skip via disposed on a metal line of a first metallization layer, and a dielectric layer disposed on sidewalls of the skip via to define an opening. The dielectric layer has uniform sidewalls from an uppermost portion of the opening to a lowermost portion of the opening.