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公开(公告)号：US20180090213A1
公开(公告)日：2018-03-29
申请号：US15828407
申请日：2017-11-30
发明人： James Peterson , Gary Janik , Jea Hyun
CPC分类号： G11C16/26 , G11C8/12 , G11C11/5642 , G11C16/20 , G11C16/3418 , G11C16/349 , G11C29/028 , G11C2029/4402 , G11C2211/5641
摘要： Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. A control module is configured to limit erase dwell times for blocks of a non-volatile memory medium to satisfy a threshold. A block classification module is configured to group blocks of a non-volatile memory medium based on retention times for the blocks. A block access module is configured to access at least one group of blocks using a read voltage threshold selected based on a grouping.
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公开(公告)号：US20180090201A1
公开(公告)日：2018-03-29
申请号：US15276588
申请日：2016-09-26
申请人： INTEL CORPORATION
发明人： Wei WU , Jawad B. KHAN , Sanjeev N. TRIKA , Yi ZOU
CPC分类号： G11C11/5628 , G06F11/1044 , G06F11/1072 , G11C11/5642 , G11C16/0483 , G11C16/3427 , G11C16/349 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller organizes the storage cells into storage cell groups, each storing m bits of information programmed with the threshold voltage levels. A determination is made of one threshold voltage level to use for each of the storage cells in the storage cell group to program a selected k bits in the storage cell group with threshold voltage levels defining one of a plurality of valid states. The threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels.
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公开(公告)号：US20180081589A1
公开(公告)日：2018-03-22
申请号：US15827189
申请日：2017-11-30
申请人： IP GEM GROUP, LLC
IPC分类号： G06F3/06
CPC分类号： G06F3/0652 , G06F3/0604 , G06F3/0688 , G06F12/00 , G11C16/0483 , G11C16/16 , G11C16/32 , G11C16/349 , G11C2216/20
摘要： A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for incrementing the number of program and erase cycles when the erase-suspend limit has been reached.
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公开(公告)号：US20180075919A1
公开(公告)日：2018-03-15
申请号：US15262262
申请日：2016-09-12
发明人： Liang Pang , Xuehong Yu , Yingda Dong , Nian Niles Yang
CPC分类号： G11C16/3495 , G11C7/14 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/28 , G11C16/3445 , G11C16/349 , H01L27/1157 , H01L27/11582
摘要： Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (Vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain the charges. However, there can be a variation in the endurance of cells even within a single die. By evaluating the dummy memory cells, an early warning can be obtained of a degradation of the data memory cells. Moreover, there is no interference with the operation of the data memory cells. Based on a number of dummy memory cells which have a Vth below a demarcation voltage, a corrective action is taken such as adjusting read voltages, an initial program voltage and/or an initial erase voltage, or marking the block as being bad and recovering the data.
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公开(公告)号：US20180068721A1
公开(公告)日：2018-03-08
申请号：US15797860
申请日：2017-10-30
CPC分类号： G11C13/004 , G11C7/06 , G11C7/065 , G11C11/1655 , G11C11/1673 , G11C13/0004 , G11C13/0026 , G11C13/0033 , G11C13/0035 , G11C13/0064 , G11C16/24 , G11C16/26 , G11C16/28 , G11C16/349 , G11C2013/0042 , G11C2013/0054 , G11C2013/0066
摘要： In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.
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46.发明申请公开(公告)号：US20180067678A1
公开(公告)日：2018-03-08
申请号：US15440680
申请日：2017-02-23
申请人： Sung-Won JEONG , Hee-Woong KANG
发明人： Sung-Won JEONG , Hee-Woong KANG
CPC分类号： G06F3/0634 , G06F1/206 , G06F3/0616 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F12/0253 , G06F2212/7205 , G11C7/04 , G11C7/109 , G11C7/222 , G11C16/349
摘要： In a method of throttling temperature of a nonvolatile memory device including a memory cell array, a current temperature of the nonvolatile memory device may be detected periodically. The current temperature may be compared with a reference temperature. Whether an external input/output command, which is provided by a memory controller, exists may be determined when the current temperature is lower than the reference temperature. An input/output operation, which corresponds to the external input/output command, may be performed on the memory cell array when the external input/output command exists. A desired and/or alternatively predetermined internal input/output operation may be performed on the memory cell array regardless of a command from the memory controller when the external input/output command does not exist.
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公开(公告)号：US09899098B1
公开(公告)日：2018-02-20
申请号：US15447123
申请日：2017-03-02
发明人： Mizuki Kaneko , Junji Musha
IPC分类号： G11C11/34 , G11C16/06 , G11C16/34 , G11C16/26 , G11C16/32 , G11C16/30 , G11C16/08 , G11C16/04
CPC分类号： G11C16/349 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3459
摘要： A semiconductor memory device includes a first word line and a second word line that are adjacent to each other, a first voltage boosting circuit configured to generate a first voltage based on a clock signal, a second voltage boosting circuit configured to generate a second voltage lower than the first voltage based on the clock signal, a counter, and a determination circuit. The counter counts a first number of clock cycles of the clock signal during a first period in which the first voltage boosting circuit generates the first voltage and applies the first voltage to the first word line while the second voltage boosting circuit generates the second voltage and applies the second voltage to the second word line, and a second number of clock cycles of the clock signal during a second period in which the first voltage boosting circuit generates the first voltage while the first word line is electrically disconnected from the first voltage boosting circuit. The determination circuit compares the first number of clock cycles and the second number of clock cycles to determine whether or not a leakage exists in the word lines.
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48.发明授权公开(公告)号：US09886214B2
公开(公告)日：2018-02-06
申请号：US15370391
申请日：2016-12-06
申请人： IP GEM GROUP, LLC
CPC分类号： G06F3/0652 , G06F3/0604 , G06F3/0688 , G06F12/00 , G11C16/0483 , G11C16/16 , G11C16/32 , G11C16/349 , G11C2216/20
摘要： A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for preventing subsequent suspends of the erase operation when the erase-suspend limit has been reached.
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49.发明申请公开(公告)号：US20180033491A1
公开(公告)日：2018-02-01
申请号：US15655639
申请日：2017-07-20
申请人： IP GEM GROUP, LLC
发明人： Alessia Marelli , Rino Micheloni
CPC分类号： G11C16/26 , G06F11/076 , G11C11/5642 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/26 , G11C29/4401 , G11C29/46 , G11C29/50004 , G11C29/50016 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , G11C2029/1202 , G11C2029/4402 , G11C2029/5002
摘要： A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, a background reference positioning circuit performs background reads of representative pages of each page group of a closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block. When a usage characteristic is determined to meet a usage characteristic threshold, a read circuit performs subsequent host-requested reads using a threshold voltage shift read instruction and reads of pages of the closed block are performed using the set of updated threshold voltage offset values corresponding to the page group of the page being read.
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公开(公告)号：US09875062B2
公开(公告)日：2018-01-23
申请号：US15061702
申请日：2016-03-04
CPC分类号： G06F3/0659 , G06F3/0616 , G06F3/0653 , G06F3/0679 , G11C7/04 , G11C16/26 , G11C16/349
摘要： A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to the determination, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.
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