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公开(公告)号：US20180107612A1
公开(公告)日：2018-04-19
申请号：US15297897
申请日：2016-10-19
IPC分类号： G06F13/16 , G06F13/364 , G06F13/42
CPC分类号： G06F13/161 , G06F13/1689 , G06F13/364 , G06F13/4291
摘要： An embodiment method includes storing, in each of a first plurality of memory locations of a memory, an address of another of the first plurality of memory locations, and reading, from a bus signal received at the memory, an address of a first one of the first plurality of memory locations. The method further includes reading data stored in the first one of the first plurality of memory locations, and determining, using the read data, whether a read error has occurred.
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公开(公告)号：US20180068721A1
公开(公告)日：2018-03-08
申请号：US15797860
申请日：2017-10-30
CPC分类号： G11C13/004 , G11C7/06 , G11C7/065 , G11C11/1655 , G11C11/1673 , G11C13/0004 , G11C13/0026 , G11C13/0033 , G11C13/0035 , G11C13/0064 , G11C16/24 , G11C16/26 , G11C16/28 , G11C16/349 , G11C2013/0042 , G11C2013/0054 , G11C2013/0066
摘要： In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.
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公开(公告)号：US09646684B1
公开(公告)日：2017-05-09
申请号：US15225898
申请日：2016-08-02
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C2013/0042 , G11C2013/0054 , G11C2013/0066
摘要： A differential PCM memory may include first and second PCM elements, and a sense amplifier circuit configured to sense a difference between first and second sense currents passing through the first and second PCM elements, respectively, during a sense operation. The differential PCM memory may include a first margin current branch coupled in parallel with the first PCM element and configured to selectively add a first margin current to the first sense current, and a second margin current branch coupled in parallel with the second PCM element and configured to selectively add a second margin current to the second sense current.
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公开(公告)号：US09991000B2
公开(公告)日：2018-06-05
申请号：US15476618
申请日：2017-03-31
CPC分类号： G11C16/24 , G11C7/065 , G11C11/161 , G11C11/1655 , G11C11/1673 , G11C13/0004 , G11C13/0026 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C13/0064 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3427 , G11C16/349 , G11C2013/0042 , G11C2013/0054 , G11C2013/0066
摘要： In accordance with an embodiment, a circuit includes a sense amplifier circuit configured to sense a difference between a first current based on a direct memory bit and a second current based on a complementary memory bit. The direct memory bit is coupled to a first input of the sense amplifier circuit, and the complementary memory bit is coupled to a second input of the sense amplifier circuit. A controller is configured to, during a sense operation, selectively add a first margin current to the first current, and during the sense operation, selectively add a second margin current to the second current.
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公开(公告)号：US20180040380A1
公开(公告)日：2018-02-08
申请号：US15476618
申请日：2017-03-31
CPC分类号： G11C16/24 , G11C7/065 , G11C11/161 , G11C11/1655 , G11C11/1673 , G11C13/0004 , G11C13/0026 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C13/0064 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3427 , G11C16/349 , G11C2013/0042 , G11C2013/0054 , G11C2013/0066
摘要： In accordance with an embodiment, a circuit includes a sense amplifier circuit configured to sense a difference between a first current based on a direct memory bit and a second current based on a complementary memory bit. The direct memory bit is coupled to a first input of the sense amplifier circuit, and the complementary memory bit is coupled to a second input of the sense amplifier circuit. A controller is configured to, during a sense operation, selectively add a first margin current to the first current, and during the sense operation, selectively add a second margin current to the second current.
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公开(公告)号：US11798630B2
公开(公告)日：2023-10-24
申请号：US17407903
申请日：2021-08-20
发明人： Marcella Carissimi , Fabio Enrico Carlo Disegni , Chantal Auricchio , Cesare Torti , Davide Manfre' , Laura Capecchi , Emanuela Calvetti , Stefano Zanchi
CPC分类号： G11C16/102 , G11C7/04 , G11C16/24 , G11C16/28 , G11C16/30
摘要： A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.
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公开(公告)号：US11049561B2
公开(公告)日：2021-06-29
申请号：US16903264
申请日：2020-06-16
发明人： Fabio Enrico Carlo Disegni , Federico Goller , Cesare Torti , Marcella Carissimi , Emanuela Calvetti
摘要： A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.
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公开(公告)号：US10319438B2
公开(公告)日：2019-06-11
申请号：US15797860
申请日：2017-10-30
摘要： In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.
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