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公开(公告)号：US11756615B2
公开(公告)日：2023-09-12
申请号：US17462250
申请日：2021-08-31
CPC分类号： G11C13/0026 , G11C13/003 , G11C13/004 , G11C13/0004 , G11C13/0038 , G06N3/02
摘要： An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.
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公开(公告)号：US11475960B2
公开(公告)日：2022-10-18
申请号：US17306266
申请日：2021-05-03
IPC分类号： G11C13/00 , G11C16/10 , G11C7/06 , G11C16/08 , G11C16/24 , G11C16/28 , G11C16/30 , G11C16/32
摘要： An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
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公开(公告)号：US20220068380A1
公开(公告)日：2022-03-03
申请号：US17462250
申请日：2021-08-31
IPC分类号： G11C13/00
摘要： An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.
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公开(公告)号：US10176869B2
公开(公告)日：2019-01-08
申请号：US16044280
申请日：2018-07-24
发明人： Marco Pasotti , Marcella Carissimi , Vikas Rana
摘要： A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.
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公开(公告)号：US20180068721A1
公开(公告)日：2018-03-08
申请号：US15797860
申请日：2017-10-30
CPC分类号： G11C13/004 , G11C7/06 , G11C7/065 , G11C11/1655 , G11C11/1673 , G11C13/0004 , G11C13/0026 , G11C13/0033 , G11C13/0035 , G11C13/0064 , G11C16/24 , G11C16/26 , G11C16/28 , G11C16/349 , G11C2013/0042 , G11C2013/0054 , G11C2013/0066
摘要： In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.
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公开(公告)号：US09646684B1
公开(公告)日：2017-05-09
申请号：US15225898
申请日：2016-08-02
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C2013/0042 , G11C2013/0054 , G11C2013/0066
摘要： A differential PCM memory may include first and second PCM elements, and a sense amplifier circuit configured to sense a difference between first and second sense currents passing through the first and second PCM elements, respectively, during a sense operation. The differential PCM memory may include a first margin current branch coupled in parallel with the first PCM element and configured to selectively add a first margin current to the first sense current, and a second margin current branch coupled in parallel with the second PCM element and configured to selectively add a second margin current to the second sense current.
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7.发明授权公开(公告)号：US09349490B2
公开(公告)日：2016-05-24
申请号：US14597824
申请日：2015-01-15
发明人： Marcella Carissimi , Marco Pasotti
IPC分类号： G11C29/00 , G11C29/52 , G11C7/18 , G11C11/56 , G11C16/04 , G11C16/26 , G11C16/28 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1048 , G11C7/18 , G11C11/5642 , G11C16/0441 , G11C16/26 , G11C16/28 , G11C2211/4013
摘要： A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.
摘要翻译： 差分存储器件包括具有直接存储单元和补充存储单元的存储单元。 相应的方法包括接收读取与所选码字相关联的所选数据字的请求，读取表示所选码字的差分版本的差分码字，根据纠错码验证差分码字，设置所选择的码字 数据字根据差分代码字响应积极的验证。 该方法还包括读取表示所选码字的单端版本的至少一个单端码字，根据纠错码验证单端码字，并根据单频码字单位设置所选择的数据字， 响应于对差分代码字的否定验证和对单端代码字的肯定验证，结束代码字。
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公开(公告)号：US20240339917A1
公开(公告)日：2024-10-10
申请号：US18746752
申请日：2024-06-18
CPC分类号： H02M1/0045 , G05F1/575 , H02M3/073 , G11C13/0004 , G11C13/0038
摘要： A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
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公开(公告)号：US20230238873A1
公开(公告)日：2023-07-27
申请号：US17582431
申请日：2022-01-24
CPC分类号： H02M1/0045 , H02M3/073 , G11C13/0004
摘要： A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
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公开(公告)号：US10109329B2
公开(公告)日：2018-10-23
申请号：US15471028
申请日：2017-03-28
摘要： A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.
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