公开(公告)号：US20170103894A1

公开(公告)日：2017-04-13

申请号：US15288349

申请日：2016-10-07

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Victorina Poenariu ,  Gerald Reinwald ,  Roland Rupp ,  Gerald Unegg

IPC: H01L21/04 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/8613

Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.

公开(公告)号：US20150069411A1

公开(公告)日：2015-03-12

申请号：US14023819

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Jens Konrath ,  Daniel Kueck ,  David Laforet ,  Cedric Ouvrard ,  Roland Rupp ,  Andreas Voerckel ,  Wolfgang Werner

IPC: H01L29/78 ,  H01L29/812 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/872

Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

Abstract translation: 根据实施例的半导体器件至少部分地布置在衬底中或衬底上，并且包括形成台面的凹部，其中台面沿着进入衬底的方向延伸到凹部的底平面，并且包括第一 导电类型，台面的半导体材料至少局部地包括不比底平面进一步延伸到衬底中的第一掺杂浓度。 所述半导体器件还包括至少部分地沿着台面的侧壁布置的导电结构，该导电结构与台面的半导体材料形成肖特基或肖特基状的电接触，其中所述衬底包括所述半导体材料的半导体材料， 所述第一导电类型至少局部地包括沿所述台面的投影到所述衬底中的与所述第一掺杂浓度不同的第二掺杂浓度。

公开(公告)号：US11626477B2

公开(公告)日：2023-04-11

申请号：US17375034

申请日：2021-07-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Thomas Basler ,  Wolfgang Bergner ,  Rudolf Elpelt ,  Romain Esteve ,  Michael Hell ,  Daniel Kueck ,  Caspar Leendertz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.

公开(公告)号：US11380756B2

公开(公告)日：2022-07-05

申请号：US16733329

申请日：2020-01-03

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Rudolf Elpelt ,  Romain Esteve ,  Thomas Ganner ,  Jens Peter Konrath ,  Larissa Wehrhahn-Kilian

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/47

Abstract: A silicon carbide device includes a silicon carbide body including a source region of a first conductivity type, a cathode region of the first conductivity type and separation regions of a second conductivity type. A stripe-shaped gate structure extends along a first direction and adjoins the source region and the separation regions. The silicon carbide device includes a first load electrode. Along the first direction, the cathode region is between two separation regions of the separation regions and at least one separation region of the separation regions is between the cathode region and the source region. The source region and the first load electrode form an ohmic contact. The first load electrode and the cathode region form a Schottky contact.

公开(公告)号：US20220059659A1

公开(公告)日：2022-02-24

申请号：US17519161

申请日：2021-11-04

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Ravi Keshav Joshi ,  Shiqin Niu

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

公开(公告)号：US11195921B2

公开(公告)日：2021-12-07

申请号：US16412131

申请日：2019-05-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Ravi Keshav Joshi ,  Shiqin Niu

IPC: H01L29/76 ,  H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

公开(公告)号：US20210118986A1

公开(公告)日：2021-04-22

申请号：US17111551

申请日：2020-12-04

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Romain Esteve ,  Florian Grasse ,  Caspar Leendertz ,  Shiqin Niu ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

公开(公告)号：US10915029B2

公开(公告)日：2021-02-09

申请号：US16153186

申请日：2018-10-05

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Rudolf Elpelt ,  Romain Esteve

IPC: H01L29/16 ,  H01L29/36 ,  H01L29/66 ,  G03F7/20 ,  H01L21/04 ,  H01J37/317 ,  H01L29/861 ,  H01L21/027 ,  H01L23/544 ,  H01L29/06

Abstract: A semiconductor device is provided that includes a silicon carbide substrate including a main surface at which a plurality of doped zones are formed in a junction termination extension zone of the silicon carbide substrate, the plurality of doped zones are arranged such that a lateral dopant concentration gradient is formed that decreases from a central region of the silicon carbide substrate to an outer edge region of the silicon carbide substrate.

公开(公告)号：US20200161433A1

公开(公告)日：2020-05-21

申请号：US16354973

申请日：2019-03-15

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Romain Esteve ,  Anton Mauder ,  Andreas Meiser ,  Bernd Zippelius

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.

公开(公告)号：US20200044076A1

公开(公告)日：2020-02-06

申请号：US16598115

申请日：2019-10-10

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Wolfgang Bergner ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L29/04 ,  H01L29/16 ,  H01L29/167 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10

Abstract: A semiconductor device includes a SiC body having a first surface, a gate trench extending from the first surface into the SiC body and having a first sidewall, a second sidewall opposite the first sidewall, and a bottom, a source region of a first conductivity type formed in the SiC body and adjoining the first sidewall of the gate trench, a drift region of the first conductivity type formed in the SiC body below the source region, a body region of a second conductivity type formed in the SiC body between the source region and the drift region and adjoining the first sidewall of the gate trench, and a diode region of the second conductivity type formed in the SiC body and adjoining the second sidewall and the bottom of the gate trench but not the first sidewall of the gate trench.