公开(公告)号：US10566426B2

公开(公告)日：2020-02-18

申请号：US15848707

申请日：2017-12-20

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Oliver Hellmund ,  Peter Irsigler ,  Jens Peter Konrath ,  David Laforet ,  Maik Langner ,  Markus Neuber ,  Hans-Joachim Schulze ,  Ralf Siemieniec ,  Knut Stahrenberg ,  Olaf Storbeck

IPC: H01L21/02 ,  H01L29/16 ,  H01L21/28 ,  H01L29/51

Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.

公开(公告)号：US09029974B2

公开(公告)日：2015-05-12

申请号：US14023819

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Jens Konrath ,  Daniel Kueck ,  David Laforet ,  Cedric Ouvrard ,  Roland Rupp ,  Andreas Voerckel ,  Wolfgang Werner

IPC: H01L29/47 ,  H01L29/78 ,  H01L29/06 ,  H01L29/812 ,  H01L29/872

CPC classification number: H01L29/7827 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/872

Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

Abstract translation: 根据实施例的半导体器件至少部分地布置在衬底中或衬底上，并且包括形成台面的凹部，其中台面沿着进入衬底的方向延伸到凹部的底平面，并且包括第一 导电类型，台面的半导体材料至少局部地包括不比底平面进一步延伸到衬底中的第一掺杂浓度。 所述半导体器件还包括至少部分地沿着台面的侧壁布置的导电结构，该导电结构与台面的半导体材料形成肖特基或肖特基状的电接触，其中所述衬底包括所述半导体材料的半导体材料， 所述第一导电类型至少局部地包括沿所述台面的投影到所述衬底中的与所述第一掺杂浓度不同的第二掺杂浓度。

公开(公告)号：US20150069411A1

公开(公告)日：2015-03-12

申请号：US14023819

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Jens Konrath ,  Daniel Kueck ,  David Laforet ,  Cedric Ouvrard ,  Roland Rupp ,  Andreas Voerckel ,  Wolfgang Werner

IPC: H01L29/78 ,  H01L29/812 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/872

Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

Abstract translation: 根据实施例的半导体器件至少部分地布置在衬底中或衬底上，并且包括形成台面的凹部，其中台面沿着进入衬底的方向延伸到凹部的底平面，并且包括第一 导电类型，台面的半导体材料至少局部地包括不比底平面进一步延伸到衬底中的第一掺杂浓度。 所述半导体器件还包括至少部分地沿着台面的侧壁布置的导电结构，该导电结构与台面的半导体材料形成肖特基或肖特基状的电接触，其中所述衬底包括所述半导体材料的半导体材料， 所述第一导电类型至少局部地包括沿所述台面的投影到所述衬底中的与所述第一掺杂浓度不同的第二掺杂浓度。