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公开(公告)号：US12057160B2
公开(公告)日：2024-08-06
申请号：US18123921
申请日：2023-03-20
Inventor： Farnood Merrikh Bayat , Xinjie Guo , Dmitri Strukov , Nhan Do , Hieu Van Tran , Vipin Tiwari , Mark Reiten
IPC: G11C11/00 , G06F3/06 , G06N3/04 , G06N3/045 , G06N3/063 , G11C11/54 , G11C16/08 , G11C16/12 , G11C16/16 , G11C16/34 , G11C29/38
CPC classification number: G11C11/54 , G06F3/061 , G06F3/0655 , G06F3/0688 , G06N3/04 , G06N3/045 , G06N3/063 , G11C16/08 , G11C16/12 , G11C16/16 , G11C16/3436 , G11C29/38
Abstract: Numerous examples of summing circuits for a neural network are disclosed. In one example, a circuit for summing current received from a plurality of synapses in a neural network comprises a voltage source; a load coupled between the voltage source and an output node; a voltage clamp coupled to the output node for maintaining a voltage at the output node; and a plurality of synapses coupled between the output node and ground; wherein an output current flows through the output node, the output current equal to a sum of currents drawn by the plurality of synapses.
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32.发明授权公开(公告)号：US12046290B2
公开(公告)日：2024-07-23
申请号：US17125459
申请日：2020-12-17
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Vipin Tiwari , Nhan Do , Mark Reiten
CPC classification number: G11C16/107 , G06N3/065 , G11C16/16
Abstract: Numerous embodiments of programming, verifying, and reading systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells can be programmed and verified with extreme precision to hold one of N different values. During a read operation, the system determines which of the N different values is stored in a selected cell.
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公开(公告)号：US12033706B2
公开(公告)日：2024-07-09
申请号：US17873739
申请日：2022-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyeong Seok , Younggul Song , Eunchu Oh , Byungchul Jang , Joonsung Lim
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/16
Abstract: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.
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公开(公告)号：US20240221841A1
公开(公告)日：2024-07-04
申请号：US18604276
申请日：2024-03-13
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki
CPC classification number: G11C16/16 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3404 , G11C16/3481
Abstract: A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and wordlines coupled with first and second pillars. Control logic may cause wordlines to be discharged after a program pulse is applied to selected wordline. The control logic may apply a supply voltage to second data line to cause a voltage of second pillar to float. The control logic may apply a ground voltage to the first data line to inhibit soft erase associated with the selected wordline via first pillar.
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公开(公告)号：US20240194270A1
公开(公告)日：2024-06-13
申请号：US18528337
申请日：2023-12-04
Applicant: Micron Technology, Inc.
Inventor： Qun Su , Pitamber Shukla , Ryan Hrinya , Fulvio Rori , Jose Nino N. Monje
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/08
Abstract: A method includes determining that a first group of word lines associated with a block of memory cells are in a programmed state and determining that a second group of word lines associated with the block of memory cells are in an unprogrammed state. The method further includes applying a first debiasing voltage to the first group of word lines based on the determination that the first group of word lines are in the programmed state and applying a second debiasing voltage to the second group of word lines based on the determination that the second group of word lines are in the unprogrammed state.
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Patent Agency Ranking
公开(公告)号：US11972795B2
公开(公告)日：2024-04-30
申请号：US18120360
申请日：2023-03-10
Inventor： Farnood Merrikh Bayat , Xinjie Guo , Dmitri Strukov , Nhan Do , Hieu Van Tran , Vipin Tiwari , Mark Reiten
IPC: G11C11/54 , G06F3/06 , G06N3/04 , G06N3/045 , G06N3/063 , G11C16/08 , G11C16/12 , G11C16/16 , G11C16/34 , G11C29/38
CPC classification number: G11C11/54 , G06F3/061 , G06F3/0655 , G06F3/0688 , G06N3/04 , G06N3/045 , G06N3/063 , G11C16/08 , G11C16/12 , G11C16/16 , G11C16/3436 , G11C29/38
Abstract: Numerous examples are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory. In one example, a circuit comprises a digital-to-analog converter to convert a target weight comprising digital bits into a target voltage, a current-to-voltage converter to convert an output current from the selected non-volatile memory cell during a verify operation into an output voltage, and a comparator to compare the output voltage to the target voltage during a verify operation.
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公开(公告)号：US11967370B1
公开(公告)日：2024-04-23
申请号：US18390193
申请日：2023-12-20
Applicant: Vervain, LLC
Inventor： G. R. Mohan Rao
CPC classification number: G11C11/5635 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G11C11/5621 , G11C11/5678 , G11C16/16 , G11C16/3495 , G11C29/52 , G11C29/76 , G06F2212/7202 , G11C2211/5641
Abstract: A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element.
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公开(公告)号：US11967369B2
公开(公告)日：2024-04-23
申请号：US18387546
申请日：2023-11-07
Applicant: Vervain, LLC
Inventor： G. R. Mohan Rao
CPC classification number: G11C11/5635 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G11C11/5621 , G11C11/5678 , G11C16/16 , G11C16/3495 , G11C29/52 , G11C29/76 , G06F2212/7202 , G11C2211/5641
Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC nonvolatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MIX and SLC nonvolatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.
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公开(公告)号：US20240127900A1
公开(公告)日：2024-04-18
申请号：US18394660
申请日：2023-12-22
Applicant: Micron Technology, Inc.
Inventor： Vamsi Rayaprolu , Ashutosh Malshe , Gary Besinga , Roy Leonard
CPC classification number: G11C16/3495 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/32
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.
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公开(公告)号：US11961570B2
公开(公告)日：2024-04-16
申请号：US16912694
申请日：2020-06-25
Applicant: Vishal Sarin , Vikram Kowshik , Purval Sule , Siraj Fulum Mossa
Inventor： Vishal Sarin , Vikram Kowshik , Purval Sule , Siraj Fulum Mossa
CPC classification number: G11C16/3459 , G06N3/063 , G11C11/54 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/0466
Abstract: In one aspect, a method for NOR flash cell-array programming in a neural circuit includes the step of erasing a cell array. The method includes the step of programming a set of reference cells of a reference cell array to a target reference threshold voltage (Vt_ref). The method includes the step of generating, with the reference cells, a current or voltage, reference signal. The method includes the step of using the reference signal to bias the neural cells during verification of program state of the neural cells to achieve their respective target threshold voltages (Vt_cell). The method includes the step of programming a set of neural cells of a neural cell array to their respective target threshold voltages.
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