公开(公告)号：US11929308B2

公开(公告)日：2024-03-12

申请号：US17515369

申请日：2021-10-29

申请人： Texas Instruments Incorporated

发明人： Steffany Ann Lacierda Moreno ,  John Carlo Cruz Molina ,  Rafael Jose Lizares Guevara

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/49548 ,  H01L21/4842 ,  H01L21/565 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/1131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/81815 ,  H01L2924/3841

摘要： In a described example, an apparatus includes: a package substrate for mounting a semiconductor die to a die side surface, the package substrate including leads spaced from one another; and cavities extending into the leads from the die side surface, the cavities having sides and a bottom surface of the lead material, the cavities at locations corresponding to post connect locations on the semiconductor die.

公开(公告)号：US20240079324A1

公开(公告)日：2024-03-07

申请号：US18503947

申请日：2023-11-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jie CHEN ,  Ying-Ju CHEN ,  Chen-Hua YU ,  Der-Chyang YEH ,  Hsien-Wei CHEN

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16235 ,  H01L2224/24147 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

摘要： A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20240071949A1

公开(公告)日：2024-02-29

申请号：US17895306

申请日：2022-08-25

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Li-Ling Liao ,  Shin-Puu Jeng

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L23/49822 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/95001 ,  H01L2924/1432 ,  H01L2924/1437 ,  H01L2924/3511 ,  H01L2924/35121

摘要： Devices and methods for forming a chip package structure including a package substrate, a first adhesive layer attached to a top surface of the package substrate, and a beveled stiffener structure attached to the package substrate. The beveled stiffener structure may include a bottom portion including a tapered top surface, in which a bottom surface of the bottom portion is in contact with the first adhesive layer, a second adhesive layer attached to the tapered top surface, and a top portion including a tapered bottom surface, in which the tapered bottom surface is in contact with the second adhesive layer. The tapered top surface and the tapered bottom surface have a taper angle between 5 degrees and 60 degrees with respect to a top surface of the package substrate.

公开(公告)号：US11916030B2

公开(公告)日：2024-02-27

申请号：US17726863

申请日：2022-04-22

申请人： PANJIT INTERNATIONAL INC.

发明人： Chung-Hsiung Ho ,  Chi-Hsueh Li

IPC分类号： H01L23/31 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/03462 ,  H01L2224/05557 ,  H01L2924/1203 ,  H01L2924/37001

摘要： A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality.

公开(公告)号：US11908795B2

公开(公告)日：2024-02-20

申请号：US17322004

申请日：2021-05-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  An-Jhih Su

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L23/528 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L23/49816 ,  H01L23/5386 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/18162 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/83005 ,  H01L2224/2919 ,  H01L2924/0665

摘要： An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via.

公开(公告)号：US11901348B2

公开(公告)日：2024-02-13

申请号：US17376865

申请日：2021-07-15

申请人： Samsung Electronics Co., Ltd.

发明人： Tae-Ho Kang ,  Bo-Seong Kim

IPC分类号： H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/16 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/24

CPC分类号： H01L25/18 ,  H01L21/4857 ,  H01L23/16 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L25/065 ,  H01L25/50 ,  H01L21/568 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2402 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/73277 ,  H01L2224/83191 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A semiconductor package includes a mold substrate, at least one first semiconductor chip in the mold substrate and including chip pads, wiring bonding pads formed at a first surface of the mold substrate and connected to the chip pads by bonding wires, and a redistribution wiring layer covering the first surface of the mold substrate and including redistribution wirings connected to the wiring bonding wirings.

公开(公告)号：US11901324B2

公开(公告)日：2024-02-13

申请号：US17451621

申请日：2021-10-20

申请人： Shanghai AVIC OPTO Electronics Co., Ltd.

发明人： Kerui Xi ,  Feng Qin ,  Jine Liu ,  Xiaohe Li ,  Tingting Cui

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/20 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/13023 ,  H01L2224/2101

摘要： Chip package structure is provided. The chip package structure includes: a chip, the chip including metal pins; an organic polymer material layer, the organic polymer material layer being located on a side of the metal pins away from the chip, the organic polymer material layer including a first via hole, and the organic polymer material layer including a first surface away from the chip; metal parts, at least a portion of the metal parts being located in the first via hole, the metal parts and metal pins being electrically connected, the metal parts including a second surface away from the chip, and the second surface and the first surface being flush to each other; and an encapsulating layer, the encapsulating layer being located on a side of the metal parts away from the organic polymer material layer.

公开(公告)号：US11901303B2

公开(公告)日：2024-02-13

申请号：US17872002

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Yen Chiu ,  Ching-Fu Chang ,  Hsin-Chieh Huang

IPC分类号： H01L23/538 ,  H01L23/66 ,  H01L49/02 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L27/146 ,  H01L23/522 ,  H01L25/00 ,  H01L25/16

CPC分类号： H01L23/5389 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/66 ,  H01L28/10 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5225 ,  H01L24/20 ,  H01L24/96 ,  H01L25/162 ,  H01L25/50 ,  H01L27/14618 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/023 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/97

摘要： An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.

公开(公告)号：US11901255B2

公开(公告)日：2024-02-13

申请号：US17869003

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chien Pan ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/3157 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657

摘要： A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.

公开(公告)号：US20240038691A1

公开(公告)日：2024-02-01

申请号：US17877426

申请日：2022-07-29

申请人： Texas Instruments Incorporated

发明人： Vijaylaxmi Gumaste Khanolkar ,  Anindya Poddar ,  Hassan Omar Ali ,  Dibyajat Mishra ,  Venkatesh Srinivasan ,  Swaminathan Sankaran

IPC分类号： H01L23/66 ,  H01Q1/22 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/66 ,  H01Q1/2283 ,  H01L21/565 ,  H01L21/561 ,  H01L24/96 ,  H01L24/97 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2223/6688 ,  H01L2924/2027 ,  H01L2924/182

摘要： In a described example, an apparatus includes: a semiconductor device mounted to a device side surface of a package substrate, the package substrate having a board side surface opposite the device side surface; an antenna module mounted to the package substrate and coupled to the semiconductor device; and mold compound covering the semiconductor device and a portion of the package substrate.