公开(公告)号：US20240079324A1

公开(公告)日：2024-03-07

申请号：US18503947

申请日：2023-11-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jie CHEN ,  Ying-Ju CHEN ,  Chen-Hua YU ,  Der-Chyang YEH ,  Hsien-Wei CHEN

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16235 ,  H01L2224/24147 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

摘要： A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20210351130A1

公开(公告)日：2021-11-11

申请号：US17366575

申请日：2021-07-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Jie CHEN ,  Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chen-Hua YU

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00

摘要： A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20190131249A1

公开(公告)日：2019-05-02

申请号：US16231735

申请日：2018-12-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Hsien HSIEH ,  Li-Han HSU ,  Wei-Cheng WU ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chi-Hsi WU

IPC分类号： H01L23/544 ,  H01L23/528 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

摘要： A method for forming a package structure and method for forming the same are provided. The method includes forming a package layer over a substrate, and forming a first dielectric layer over the package layer. The method further includes forming a first alignment mark and a second alignment mark over the first dielectric layer. The method includes forming a second dielectric layer over the first dielectric layer and removing a portion of the second dielectric layer to form a first trench to expose the first alignment mark, and to form a first opening to expose the second alignment.

公开(公告)号：US20200286830A1

公开(公告)日：2020-09-10

申请号：US16883210

申请日：2020-05-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jie CHEN ,  Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chen-Hua YU

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00

摘要： A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20180005955A1

公开(公告)日：2018-01-04

申请号：US15200747

申请日：2016-07-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Hsien HSIEH ,  Li-Han HSU ,  Wei-Cheng WU ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chi-Hsi WU

IPC分类号： H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528

CPC分类号： H01L23/544 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/528 ,  H01L24/14 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/18 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074

摘要： A package structure and method for forming the same are provided. The package structure includes a substrate and a package layer formed over the substrate. The package structure further includes an alignment structure formed over the package layer, and the alignment structure includes a first alignment mark formed in a trench, and the trench has a step-shaped structure.