公开(公告)号：US20110316141A1

公开(公告)日：2011-12-29

申请号：US12822601

申请日：2010-06-24

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC: H01L23/485 ,  H01L21/60 ,  H01L21/822

CPC classification number: H01L21/6835 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2746 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32148 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/83121 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2221/68304

Abstract: A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip.

Abstract translation: 分层芯片封装包括主体和布置在主体的侧表面上的布线。 主体包括：主要部分，其包括堆叠的多个层部分; 多个第一端子，其设置在所述主体部的上表面并与所述布线连接; 以及多个第二端子，其设置在所述主体部的底面并与所述布线连接。 多个层部分包括第一类型层部分和第二类型部分。 第一型层部分包括符合半导体芯片和连接到半导体芯片和布线的多个第一类型电极。 第二型层部分包括有缺陷的半导体芯片，以及多个第二类型电极，其连接到布线而不连接到半导体芯片。

公开(公告)号：US20110222252A1

公开(公告)日：2011-09-15

申请号：US12835917

申请日：2010-07-14

Applicant: Kong-Chen Chen

Inventor： Kong-Chen Chen

IPC: H05K1/18

CPC classification number: H01L22/34 ,  H01L22/32 ,  H01L23/04 ,  H01L23/544 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29444 ,  H01L2224/7532 ,  H01L2224/75703 ,  H01L2224/75753 ,  H01L2224/75988 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

Abstract: The present invention provides systems and methods for assembling an electronic assembly using an anisotropic conducting membrane (ACM) as a component interconnect and a substrate embossed with placement cavities or a positional fixture to facilitate component placement on the substrate in the electronic assembly. The fixture may comprise multiple layers of interconnects to improve routing density for the electronic assembly enclosed in a housing. An alignment chain may be used to monitor positional and contact integrity of the ACM interfaced components in a complex assembly. The systems and methods allow components to be detached for reuse. Interconnection elements or conduction pathways at the components can be used to interconnect a plurality of neighboring substrates over the ACM layers into a stacked electronic assembly.

公开(公告)号：US20240332249A1

公开(公告)日：2024-10-03

申请号：US18536865

申请日：2023-12-12

Applicant: Samsung Display Co., LTD.

Inventor： JEONGMIN BAE ,  SUNGLAE KIM ,  JUNSEOK AHN ,  YEONGHO HA

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/75 ,  H01L2224/75701 ,  H01L2224/75753 ,  H01L2224/75804 ,  H01L2224/8313

Abstract: Provided is a bonding apparatus. The bonding apparatus includes a first stage on which a display panel including a first mark is disposed, a pressing part disposed above the first stage and configured to provide a data driver including a second mark on the display panel, and an alignment camera disposed below the first stage. When the data driver is provided on the display panel such that the data driver and the display panel are connected to each other, the alignment camera is configured to capture images of the first mark and the second mark at a same temporal instance.

公开(公告)号：US20230197625A1

公开(公告)日：2023-06-22

申请号：US17556149

申请日：2021-12-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TSE-YAO HUANG

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L23/5386 ,  H01L23/5222 ,  H01L24/32 ,  H01L24/83 ,  H01L2223/54426 ,  H01L2225/06593 ,  H01L2224/32145 ,  H01L2224/32057 ,  H01L2224/8313

Abstract: The present application discloses a semiconductor device with integrated decoupling alignment features. The semiconductor device includes a first wafer comprising a first substrate having a dielectric stack, a decoupling feature positioned in the dielectric stack under one of the plurality of first alignment marks, a plurality of first alignment marks positioned on the first substrate and parallel to each other; and a second wafer positioned on the first wafer and comprising a plurality of second alignment marks positioned above the plurality of first alignment marks. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks in a top-view perspective. The plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescence material. The decoupling feature has a is bottle-shaped cross-sectional profile, and the decoupling feature comprises a porous low-k material.

公开(公告)号：US20190206831A1

公开(公告)日：2019-07-04

申请号：US16247957

申请日：2019-01-15

Applicant: DEXERIALS CORPORATION

Inventor： Yasushi AKUTSU

IPC: H01L23/00 ,  C09J9/02 ,  G02F1/1345 ,  H01L23/544 ,  C09J7/00 ,  H05K1/02 ,  H05K3/32 ,  C09D163/00

CPC classification number: H01L24/83 ,  C08K2201/001 ,  C09D163/00 ,  C09J7/00 ,  C09J7/10 ,  C09J9/02 ,  C09J171/12 ,  C09J2203/326 ,  C09J2205/102 ,  G02F1/13306 ,  G02F1/1339 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13452 ,  G02F2001/133302 ,  G02F2001/133354 ,  G02F2202/28 ,  H01L23/544 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/91 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29357 ,  H01L2224/2936 ,  H01L2224/29371 ,  H01L2224/2939 ,  H01L2224/294 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83101 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H05K1/0269 ,  H05K3/323 ,  H05K2203/166 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: An alignment mark at a position that overlaps an area in which an anisotropic conductive film is pasted, and to accurately perform alignment using an image captured by a camera. An alignment method in which an electronic component is mounted on the obverse surface of a transparent substrate with a conductive adhesive agent interposed therebetween, a substrate-side alignment mark and a component-side alignment mark are adjusted from the captured image, and the position at which the electronic component is mounted on the transparent substrate is aligned, wherein in the conductive adhesive agent, conductive particles are in a regular arrangement as viewed from a planar perspective, and in the captured image, the outside edges of the alignment marks exposed between the conductive particles are intermittently visible as line segments (S) along the imaginary line segments of the outside edges of the alignment mark.

公开(公告)号：US09793221B2

公开(公告)日：2017-10-17

申请号：US15009969

申请日：2016-01-29

Applicant: FUJITSU LIMITED

Inventor： Hidehiko Kira ,  Norio Kainuma ,  Takashi Kubota ,  Takumi Masuyama

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L23/544 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/27334 ,  H01L2224/27436 ,  H01L2224/27632 ,  H01L2224/2783 ,  H01L2224/279 ,  H01L2224/29011 ,  H01L2224/29018 ,  H01L2224/29019 ,  H01L2224/29076 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/3201 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75301 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/273 ,  H01L21/78

Abstract: A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal is embedded inside the first insulating film. The second insulating film is formed on a joining target face of a joining target, which includes a connection target terminal on the joining target face, and the connection target terminal is embedded inside the second insulating film. The semiconductor device and the joining target are joined together by applying pressure and causing the semiconductor device and the joining target to make contact with each other.

公开(公告)号：US20170236795A1

公开(公告)日：2017-08-17

申请号：US15584609

申请日：2017-05-02

Applicant: DEXERIALS CORPORATION

Inventor： Kenichi SARUYAMA ,  Yasushi AKUTSU

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/2929 ,  H01L2224/29293 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/2936 ,  H01L2224/29387 ,  H01L2224/29388 ,  H01L2224/2939 ,  H01L2224/294 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81488 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83499 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/0549 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/066 ,  H01L2924/069 ,  H01L2924/0635 ,  H01L2924/01006

Abstract: Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched between each main surface of the substrate electrodes and electrode terminals are sufficiently compressed, ensuring electrical conduction. An electronic component is connected to a circuit substrate via an anisotropic conductive adhesive agent, on respective edge-side areas of substrate electrodes of the circuit substrate and electrode terminals of the electronic component, stepped sections are formed and abutted, conductive particles are sandwiched between each main surface and stepped sections of the substrate electrodes and electrode terminals; the conductive particles and stepped sections satisfy formula, a+b+c≦0.8 D (1), wherein a is height of the stepped section of the electrode terminals, b is height of the stepped section of the substrate electrodes, c is gap distance between each stepped sections and D is diameter of conductive particles.

公开(公告)号：US20170084581A1

公开(公告)日：2017-03-23

申请号：US15252454

申请日：2016-08-31

Applicant: FUJITSU LIMITED

Inventor： Shunichi Kikuchi ,  Hiroshi Onuki ,  Naoaki Nakamura ,  Yoshihisa IWAKIRI

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/544

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29078 ,  H01L2224/29287 ,  H01L2224/2929 ,  H01L2224/3201 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8109 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8309 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/3301 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/0549 ,  H01L2924/0531 ,  H01L2924/01001 ,  H01L2924/0532 ,  H01L2924/01012 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/05032 ,  H01L2224/33051

Abstract: A laminated chip includes: semiconductor chips that are laminated; and multiple types of adhesive insulating resin films that include mutually different characteristics and that are filled between the semiconductor chips, wherein the multiple types of the adhesive insulating resin films are arranged in a chip plane direction, depending on a demand characteristic for each region in a chip plane.

公开(公告)号：US20160351532A1

公开(公告)日：2016-12-01

申请号：US15117326

申请日：2015-02-03

Applicant: DEXERIALS CORPORATION

Inventor： Yasushi AKUTSU

IPC: H01L23/00 ,  C09J9/02 ,  C09J171/12

CPC classification number: H01L24/83 ,  C08K2201/001 ,  C09D163/00 ,  C09J7/00 ,  C09J7/10 ,  C09J9/02 ,  C09J171/12 ,  C09J2203/326 ,  C09J2205/102 ,  G02F1/13306 ,  G02F1/1339 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1345 ,  G02F1/13452 ,  G02F2001/133302 ,  G02F2001/133354 ,  G02F2202/28 ,  H01L23/544 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/91 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29357 ,  H01L2224/2936 ,  H01L2224/29371 ,  H01L2224/2939 ,  H01L2224/294 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83101 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H05K1/0269 ,  H05K3/323 ,  H05K2203/166 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: An alignment mark at a position that overlaps an area in which an anisotropic conductive film is pasted, and to accurately perform alignment using an image captured by a camera. An alignment method in which an electronic component is mounted on the obverse surface of a transparent substrate with a conductive adhesive agent interposed therebetween, a substrate-side alignment mark and a component-side alignment mark are adjusted from the captured image, and the position at which the electronic component is mounted on the transparent substrate is aligned, wherein in the conductive adhesive agent, conductive particles are in a regular arrangement as viewed from a planar perspective, and in the captured image, the outside edges of the alignment marks exposed between the conductive particles are intermittently visible as line segments (S) along the imaginary line segments of the outside edges of the alignment mark.

Abstract translation: 在与各向异性导电膜被粘贴的区域重叠的位置处的对准标记，并且使用由照相机拍摄的图像来精确地进行对准。 将电子部件安装在透明基板的具有导电性粘合剂的正面的基板侧对准标记和分量侧对准标记的对准方法中，从捕获图像和位置 对准电子部件安装在透明基板上，其中在导电粘合剂中，从平面的角度看，导电颗粒处于规则的布置，并且在捕获的图像中，对准标记的外边缘在 导电颗粒沿着对准标记的外边缘的假想线段间断地看作线段（S）。

公开(公告)号：US20160351531A1

公开(公告)日：2016-12-01

申请号：US15114453

申请日：2015-02-03

Applicant: DEXERIALS CORPORATION

Inventor： Kenichi SARUYAMA ,  Yasushi AKUTSU

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/2929 ,  H01L2224/29293 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/2936 ,  H01L2224/29387 ,  H01L2224/29388 ,  H01L2224/2939 ,  H01L2224/294 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81488 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83499 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/0549 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/066 ,  H01L2924/069 ,  H01L2924/0635 ,  H01L2924/01006

Abstract: Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched between each main surface of the substrate electrodes and electrode terminals are sufficiently compressed, ensuring electrical conduction. An electronic component is connected to a circuit substrate via an anisotropic conductive adhesive agent, on respective edge-side areas of substrate electrodes of the circuit substrate and electrode terminals of the electronic component, stepped sections are formed and abutted, conductive particles are sandwiched between each main surface and stepped sections of the substrate electrodes and electrode terminals; the conductive particles and stepped sections satisfy formula, a+b+c≦0.8 D (1), wherein a is height of the stepped section of the electrode terminals, b is height of the stepped section of the substrate electrodes, c is gap distance between each stepped sections and D is diameter of conductive particles.

Abstract translation: 即使在基板电极和电极端子的台阶部之间夹着导电粒子的情况下，夹在基板电极的每个主表面和电极端子之间的导电颗粒被充分地压缩，从而确保导电。 电子部件通过各向异性导电粘合剂在电路基板的基板电极的各个边缘侧区域和电子部件的电极端子上连接到电路基板，台阶部形成并抵接，导电粒子夹在每个 基板电极和电极端子的主表面和阶梯部分; 导电粒子和阶梯部分满足公式a + b +c≤0.8D（1）其中a是电极端子的阶梯部分的高度，b是基板电极的阶梯部分的高度，c是间隙距离 在每个阶梯部分之间，D是导电颗粒的直径。