公开(公告)号：US10453522B2

公开(公告)日：2019-10-22

申请号：US15487526

申请日：2017-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Carlos H. Diaz ,  Chih-Hao Wang ,  Jean-Pierre Colinge ,  Ta-Pen Guo

IPC: G11C11/21 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11582 ,  H01L49/02

Abstract: Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.

公开(公告)号：US10193090B2

公开(公告)日：2019-01-29

申请号：US15627722

申请日：2017-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Jean-Pierre Colinge ,  Ken-Ichi Goto ,  Zhiqiang Wu ,  Yu-Ming Lin

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

公开(公告)号：US09865655B2

公开(公告)日：2018-01-09

申请号：US14970001

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L27/2454 ,  G11C7/04 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/53 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1683

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a memory cell structure formed over the substrate. In addition, the memory cell structure includes a first electrode layer formed over the substrate and a resistance-change material layer formed over the first electrode layer. The memory cell structure further includes a second electrode layer formed over the resistance-change material layer. In addition, the resistance-change material layer includes a semimetal or a semimetal alloy.

公开(公告)号：US09853150B1

公开(公告)日：2017-12-26

申请号：US15236541

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre Colinge ,  Ken-Ichi Goto ,  ZhiQiang Wu

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/785

Abstract: A method of fabricating epitaxial gate dielectric includes forming a SrxBayMzTiO3 gate dielectric on a fin, and 0≦x, y and z≦1, x+y+z=1, and M is calcium or magnesium. One of x and y is not 0. The SrxBayMzTiO3 gate dielectric includes a plurality of SrxBayMzTiO3 dielectric films. Each of the SrxBayMzTiO3 dielectric films has different ratio of x, y, and z. The fin is then oxidized to form a silicon oxide in between the SrxBayMzTiO3 gate dielectric and the fin. A dielectric layer is disposed on the SrxBayMzTiO3 gate dielectric. Subsequently a metal gate layer is deposited on the dielectric layer.

公开(公告)号：US09659632B2

公开(公告)日：2017-05-23

申请号：US14918068

申请日：2015-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Ta-Pen Guo ,  Carlos H. Diaz ,  Chih-Hao Wang ,  Jean-Pierre Colinge

IPC: G11C11/41 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L27/11582 ,  H01L28/00

Abstract: Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.

公开(公告)号：US09653604B1

公开(公告)日：2017-05-16

申请号：US15058672

申请日：2016-03-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/45 ,  H01L21/02 ,  H01L21/465

CPC classification number: H01L21/28518 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/465 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.

公开(公告)号：US11854905B2

公开(公告)日：2023-12-26

申请号：US17814692

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jin-Aun Ng ,  Kuo-Cheng Chiang ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  B82Y40/00 ,  H01L29/16 ,  H01L29/78 ,  B82Y10/00

CPC classification number: H01L21/823821 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78696 ,  H01L29/6681

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.

公开(公告)号：US11532705B2

公开(公告)日：2022-12-20

申请号：US16921606

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Ta-Pen Guo

IPC: H01L29/06 ,  H01L29/792 ,  H01L29/775 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L27/06 ,  H01L27/11578 ,  B82Y10/00 ,  G06F3/06 ,  G11C13/02 ,  G11C14/00 ,  G11C15/04 ,  H01L27/11514 ,  H01L29/78

Abstract: Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.

公开(公告)号：US20220359309A1

公开(公告)日：2022-11-10

申请号：US17814692

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jin-Aun Ng ,  Kuo-Cheng Chiang ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L21/8238 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L27/092 ,  H01L29/16 ,  H01L29/78 ,  B82Y10/00

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.

公开(公告)号：US20220238704A1

公开(公告)日：2022-07-28

申请号：US17717799

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L29/267 ,  H01L29/78 ,  H01L27/088 ,  H01L29/04 ,  H01L21/02 ,  H01L29/10 ,  H01L21/477 ,  H01L21/8234 ,  H01L21/8256 ,  H01L29/786 ,  H01L27/06 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/423 ,  H01L21/426 ,  H01L21/441 ,  H01L21/461 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/24

Abstract: Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.