公开(公告)号：US09633929B2

公开(公告)日：2017-04-25

申请号：US14933583

申请日：2015-11-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ku-Feng Yang ,  Shin-Puu Jeng ,  Wen-Chih Chiou

IPC分类号： H01L23/48 ,  H01L23/532 ,  H01L21/288 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L21/288 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014

摘要： A device includes a substrate having a front side and a backside, the backside being opposite the front side. An isolation layer is disposed on the front side of the substrate, wherein first portions of isolation layer and the substrate are in physical contact. A through substrate via (TSV) extends from the front side to the backside of the substrate. An oxide liner is on a sidewall of the TSV. The oxide liner extends between second portions of the substrate and the isolation layer. A dielectric layer having a metal pad is disposed over the isolation layer on the front side of the substrate. The metal pad and the TSV are formed of a same material.

公开(公告)号：US20170011988A1

公开(公告)日：2017-01-12

申请号：US15269753

申请日：2016-09-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Chi Lin ,  Hsin-Yu Chen ,  Ming-Tsu Chung ,  HsiaoYun Lo ,  Hong-Ye Shih ,  Chia-Yin Chen ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/76841 ,  H01L21/76883 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

摘要翻译： 半导体器件包括从半导体基板延伸到半导体基板的背面的贯通基板。 贯通基板通孔包括与半导体基板的背面相邻的凹部或凸部。 隔离膜形成在半导体衬底的背面。 导电层包括形成在穿通基板通孔的凹部或凸部上的第一部分和形成在隔离膜上的第二部分。 钝化层部分地覆盖导电层。

公开(公告)号：US09514986B2

公开(公告)日：2016-12-06

申请号：US14012108

申请日：2013-08-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Chi Lin ,  Yen-Hung Chen ,  Yin-Hua Chen ,  Ebin Liao ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76898 ,  H01L21/76849 ,  H01L23/481 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure.

摘要翻译： 一种包括在半导体衬底上的第一介电层，形成在第一介电层中的栅电极和穿透第一介电层并延伸到半导体衬底中的贯穿衬底通孔（TSV）结构的器件。 TSV结构包括导电层，围绕导电层的扩散阻挡层和围绕扩散阻挡层的隔离层。 包含钴的覆盖层形成在TSV结构的导电层的顶表面上。

公开(公告)号：US20160240439A1

公开(公告)日：2016-08-18

申请号：US14622420

申请日：2015-02-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Hung-Pin Chang ,  Yi-Hsiu Chen ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC分类号： H01L21/78 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L21/304

CPC分类号： H01L21/78 ,  H01L21/02057 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L24/97 ,  H01L2224/95

摘要： A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.

摘要翻译： 提供半导体器件和制造方法。 在一个实施例中，第一半导体器件和第二半导体器件形成在半导体晶片内，并且在第一半导体器件和第二半导体器件之间的刻划区域被图案化。 然后在划线区域内利用单个处理从第二半导体器件对第一半导体器件进行分割。 然后将第一半导体器件和第二半导体器件接合到第二半导体衬底并变薄以从第一半导体器件和第二半导体器件去除延伸区域。

公开(公告)号：US20150318263A1

公开(公告)日：2015-11-05

申请号：US14462791

申请日：2014-08-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Sen Lu ,  Wen-Chih Chiou ,  Wen-Ching Tsai

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/3114 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/80 ,  H01L24/81 ,  H01L24/82 ,  H01L24/89 ,  H01L24/92 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/20 ,  H01L2224/24146 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06544 ,  H01L2924/01014 ,  H01L2924/05442 ,  H01L2924/37 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/80001 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2224/8203

摘要： Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.

摘要翻译： 本文公开了一种包括第一管芯，其具有设置在第一基板的第一侧上的第一再分布层（RDL）和具有设置在第二基板的第一侧上的第二RDL的第二管芯，其中第一RDL结合到 第二个RDL。 具有第三RDL的第三模具设置在第三基板的第一侧上，第三模具安装在第二模具上，第二模具设置在第一模具和第三模具之间。 第一通孔延伸通过并与第二基板电隔离，第一通孔各自接触第一RDL或第二RDL中的导电元件。 第二通孔延伸通过第三基板并且与第三基板电隔离，第二通孔各自接触第三RDL中的导电元件或第一通孔中的一个。

公开(公告)号：US09159673B2

公开(公告)日：2015-10-13

申请号：US14204722

申请日：2014-03-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jung Cheng Ko ,  Chi-Chun Hsieh ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532 ,  H01L23/525 ,  H01L23/00

CPC分类号： H01L23/5384 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49883 ,  H01L23/525 ,  H01L23/5328 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.

摘要翻译： 形成器件的方法包括在电介质片上印刷导电图案以形成预先印墨的片材，以及将预印墨片材粘合到基片的一侧上。 导电特征包括从衬底的第一主侧延伸到与第一主侧相对的衬底的第二主侧的贯通衬底。 然后施加导电膏以将导电图案电耦合到衬底中的导电特征。

公开(公告)号：US20150235940A1

公开(公告)日：2015-08-20

申请号：US14685023

申请日：2015-04-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yu Chen ,  Ku-Feng Yang ,  Tasi-Jung Wu ,  Lin-Chih Huang ,  Yuan-Hung Liu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L23/528 ,  H01L27/06 ,  H01L23/538 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/76807 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5384 ,  H01L27/0617 ,  H01L2221/1031 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/00

摘要： An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first photo-sensitive dielectric layer formed over the interlayer dielectric layer, wherein the first photo-sensitive dielectric layer comprises a first metal structure and a second photo-sensitive dielectric layer formed over the first photo-sensitive dielectric, wherein the second photo-sensitive dielectric layer comprises a second metal structure having a bottom surface coplanar with a top surface of the first metal structure.

摘要翻译： 一种装置包括形成在衬底的第一侧上的层间介质层，形成在层间电介质层上的第一光敏电介质层，其中第一光敏电介质层包括第一金属结构和第二光敏电介质 所述第二光敏电介质层包括具有与所述第一金属结构的顶表面共面的底表面的第二金属结构。

公开(公告)号：US20150221611A1

公开(公告)日：2015-08-06

申请号：US14257833

申请日：2014-04-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shin-Puu Jeng ,  Wen-Chih Chiou ,  Tu-Hao Yu ,  Hung-Jung Tu ,  Yu-Liang Lin ,  Shih-Hui Wang

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC分类号： H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13811 ,  H01L2224/13816 ,  H01L2224/13839 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/80805 ,  H01L2224/81805 ,  H01L2224/83 ,  H01L2224/83192 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/161 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

摘要： Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies.

摘要翻译： 公开了封装半导体器件和封装半导体器件的方法。 在一些实施例中，封装半导体器件的方法包括将集成电路管芯耦合到衬底，以及将模制材料设置在集成电路管芯周围。 盖层设置在成型材料和多个集成电路管芯之上。

公开(公告)号：US09087878B2

公开(公告)日：2015-07-21

申请号：US13960171

申请日：2013-08-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ebin Liao ,  Tsang-Jiuh Wu

IPC分类号： H01L21/44 ,  H01L21/311 ,  H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L21/76831 ,  H01L21/486 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00

摘要： A method includes forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth. The method further includes forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening and forming a conductive layer on the insulation structure to fill the opening. A first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

摘要翻译： 一种方法包括形成从硅衬底的顶表面延伸到硅衬底到预定深度的开口。 该方法还包括沿着开口的侧壁和底部在硅衬底上形成绝缘结构，并在绝缘结构上形成一个填充开口的导电层。 绝缘结构和硅衬底之间的第一接口具有峰 - 谷高度小于5nm的界面粗糙度，并且绝缘结构和导电层之间的第二界面具有峰 - 谷高度小于5nm。

公开(公告)号：US08802504B1

公开(公告)日：2014-08-12

申请号：US13938939

申请日：2013-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shang-Yun Hou ,  Sao-Ling Chiu ,  Ping-Kang Huang ,  Wen Hsin Wei ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Bruce C. S. Chou

IPC分类号： H01L21/44

CPC分类号： H01L24/17 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/44 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0382 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/1182 ,  H01L2224/13 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00

摘要： Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.

摘要翻译： 本公开的实施例包括半导体器件和形成半导体器件的方法。 一个实施例是一种形成半导体器件的方法，所述方法包括在第一衬底中形成导电焊盘，在导电焊盘和第一衬底之上形成互连结构，所述互连结构包括多个设置在多个 介电层，将管芯连接到互连结构的第一侧，并且从互连结构的第二侧蚀刻第一衬底，蚀刻暴露导电焊盘的一部分。