公开(公告)号：US20170110374A1

公开(公告)日：2017-04-20

申请号：US15198763

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Da Yang ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L21/823821 ,  H01L21/02118 ,  H01L21/022 ,  H01L21/823431 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853

Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.

公开(公告)号：US09502283B2

公开(公告)日：2016-11-22

申请号：US14627653

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Da Yang ,  Choh Fei Yeap

IPC: H01L21/768 ,  G06F17/50 ,  H01L21/311 ,  H01L23/535 ,  G03F1/00 ,  G03F7/20

CPC classification number: H01L21/76802 ,  G03F1/14 ,  G03F7/203 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/7045 ,  G03F7/70466 ,  G06F17/5077 ,  H01L21/31116 ,  H01L23/535

Abstract: Electron-beam (e-beam) based semiconductor device features are disclosed. In a particular aspect, a method includes performing a first lithography process to fabricate a first set of cut pattern features on a semiconductor device. A distance of each feature of the first set of cut pattern features from the feature to an active area is greater than or equal to a threshold distance. The method further includes performing an electron-beam (e-beam) process to fabricate a second cut pattern feature on the semiconductor device. A second distance of the second cut pattern feature from the second cut pattern feature to the active area is less than or equal to the threshold distance.

Abstract translation: 公开了基于电子束（e-beam）的半导体器件特征。 在特定方面，一种方法包括执行第一光刻工艺以在半导体器件上制造第一组切割图案特征。 从特征到有效区域的第一组切割图案特征的每个特征的距离大于或等于阈值距离。 该方法还包括执行电子束（e-beam）工艺以在半导体器件上制造第二切割图案特征。 第二切割图案特征从第二切割图案特征到有效区域的第二距离小于或等于阈值距离。

公开(公告)号：US10700204B2

公开(公告)日：2020-06-30

申请号：US16104522

申请日：2018-08-17

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/165

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US10090244B2

公开(公告)日：2018-10-02

申请号：US15634039

申请日：2017-06-27

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Da Yang ,  Periannan Chidambaram

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L27/02 ,  G06F17/50 ,  H01L27/118

Abstract: Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect ratio voltage rail configured to receive a first supply voltage. A second high aspect ratio voltage rail is employed that is disposed substantially parallel to the first high aspect ratio voltage rail. A voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. The first and second high aspect ratio voltage rails each have a height-to-width ratio greater than 1.0. The height of each respective first and second high aspect ratio voltage rail is greater than each respective width. Employing the first and second high aspect ratio voltage rails allows each to have a cross-sectional area that limits the resistance and corresponding IR drop.

公开(公告)号：US09997360B2

公开(公告)日：2018-06-12

申请号：US15271867

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Da Yang ,  Yanxiang Liu ,  Jun Yuan ,  Kern Rim

IPC: H01L29/76 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US09985014B2

公开(公告)日：2018-05-29

申请号：US15266523

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Da Yang

IPC: G06F17/50 ,  H01L27/00 ,  H01L27/02 ,  H01L29/423

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L27/11807 ,  H01L29/4232 ,  H01L2027/11811

Abstract: Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.

公开(公告)号：US20170110541A1

公开(公告)日：2017-04-20

申请号：US15198892

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Da Yang ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/0673 ,  H01L21/02603 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/125 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: Aspects disclosed in the detailed description include nanowire channel structures of continuously stacked heterogeneous nanowires for complementary metal oxide semiconductor (CMOS) devices. Each of the nanowires has a top end portion and a bottom end portion that are narrower than a central portion. Furthermore, vertically adjacent nanowires are interconnected at the narrower top end portions and bottom end portions. This allows for connectivity between stacked nanowires and for having separation areas between vertically adjacent heterogeneous nanowires. Having the separation areas allows for gate material to be disposed over a large area of the heterogeneous nanowires and, therefore, provides strong gate control, a shorter nanowire channel structure, low parallel plate parasitic capacitance, and low parasitic channel capacitance. Having the nanowires be heterogeneous, i.e., fabricated using materials of different etching sensitivity, facilitates forming the particular cross section of the nanowires, thus eliminating the use of sacrificial masks/layers to form the heterogeneous nanowires.

公开(公告)号：US20160233159A1

公开(公告)日：2016-08-11

申请号：US14855939

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Niladri Narayan Mojumder ,  Da Yang ,  Choh Fei Yeap

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: In a particular aspect, an apparatus includes a first via of an integrated circuit. The apparatus includes a second via of the integrated circuit. The apparatus includes a first via connector coupled to the first via. The apparatus includes a second via connector coupled to the second via. The apparatus further includes a metal structure separated from and encircling the first via connector and the second via connector.

Abstract translation: 在特定方面，一种装置包括集成电路的第一通孔。 该装置包括集成电路的第二通孔。 该装置包括耦合到第一通孔的第一通孔连接器。 该装置包括耦合到第二通孔的第二通孔连接器。 该设备还包括与第一通孔连接器和第二通孔连接器分离并包围的金属结构。

公开(公告)号：US20160141250A1

公开(公告)日：2016-05-19

申请号：US14660544

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Da Yang ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L23/532 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/32051 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76864 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a dielectric material and an interconnect structure. The semiconductor device further includes a barrier layer positioned between the dielectric material and the interconnect structure. The barrier layer includes two or more metals. Each metal of the two or more metals of the barrier layer is phase segregated from each other metal of the two or more metals.

Abstract translation: 半导体器件包括电介质材料和互连结构。 半导体器件还包括位于介电材料和互连结构之间的阻挡层。 阻挡层包括两种或更多种金属。 阻挡层的两种或更多种金属的每种金属与两种或更多种金属的彼此金属相分离。

公开(公告)号：US20160079175A1

公开(公告)日：2016-03-17

申请号：US14484366

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Kern Rim ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Da Yang

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53257 ,  H01L21/0217 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via are disclosed. Related methods are also disclosed. In particular, different metal lines in a metal layer may need to be electrically interconnected during a MOL process for an IC. In this regard, to allow for metal lines to be interconnected without providing such interconnections above the metal lines that may be difficult to provide in a printing process for example, in an exemplary aspect, an elongated or expanded via(s) is provided in a MOL layer in an IC. The elongated via is provided in the MOL layer below the metal layer in the MOL layer and extended across two or more adjacent metal layers in the metal layer of the MOL layer. Moving the interconnections above the MOL layer can simplify the manufacturing of ICs, particularly at low nanometer (nm) node sizes.

Abstract translation: 公开了采用使用细长通孔的金属线的局部互连的中线（MOL）制造的集成电路（IC）。 还公开了相关方法。 特别地，金属层中的不同金属线可能需要在IC的MOL工艺期间电连接。 在这方面，为了允许金属线互连，而不在例如在示例性方面中在印刷过程中难以提供的金属线上方提供这样的互连，在一个或多个金属线中提供细长或扩张的通孔 IC中的MOL层。 细长通道设置在MOL层中的金属层下方的MOL层中，并且延伸穿过MOL层的金属层中的两个或更多个相邻的金属层。 移动MOL层上方的互连可以简化IC的制造，特别是在纳米（nm）节点尺寸较小的情况下。