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    SILICON GERMANIUM READ PORT FOR A STATIC RANDOM ACCESS MEMORY REGISTER FILE
    32.
    发明申请
    SILICON GERMANIUM READ PORT FOR A STATIC RANDOM ACCESS MEMORY REGISTER FILE 有权
    SILICON GERMANIUM读端口，用于静态随机存取存储器寄存器文件

    公开(公告)号：US20160064068A1

    公开(公告)日：2016-03-03

    申请号：US14473974

    申请日：2014-08-29

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C11/405 ,  G11C11/409 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054

    Abstract: A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.

    Abstract translation: 静态随机存取存储器（SRAM）电路包括耦合到写入端口的写入端口和读取端口。 读端口包括读位线和具有硅锗（SiGe）沟道的第一p型金属氧化物半导体（PMOS）晶体管。 读端口还包括具有第二SiGe沟道的第二PMOS晶体管，其中第二PMOS晶体管耦合到第一PMOS晶体管。

    Via material selection and processing
    35.
    发明授权
    Via material selection and processing 有权
    通过材料选择和处理

    公开(公告)号：US09196583B1

    公开(公告)日：2015-11-24

    申请号：US14274470

    申请日：2014-05-09

    Applicant: QUALCOMM Incorporated

    Inventor： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Kern Rim ,  Zhongze Wang

    IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5228 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material.

    Abstract translation: 用于半导体互连的半导体互连和方法。 互连可以包括在第一导电互连层和第一中间线（MOL）互连层之间的第一导电材料的第一通孔。 第一个MOL互连层位于第一层。 第一个通孔用单个镶嵌工艺制造。 这种半导体互连还包括在第一导电互连层和第二MOL互连层之间的第二导电材料的第二通孔。 第二个MOL互连层位于第二层。 第二个通孔用双镶嵌工艺制造。 第一导电材料与第二导电材料不同。

    Static random access memories (SRAM) with read-preferred cell structures, write drivers, related systems, and methods
    36.
    发明授权
    Static random access memories (SRAM) with read-preferred cell structures, write drivers, related systems, and methods 有权
    具有读优选单元结构的静态随机存取存储器（SRAM），写入驱动器，相关系统和方法

    公开(公告)号：US09111635B2

    公开(公告)日：2015-08-18

    申请号：US13869110

    申请日：2013-04-24

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Zhongze Wang ,  Choh fei Yeap

    IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

    CPC classification number: G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104 ,  Y10T29/41

    Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

    Abstract translation: 公开了具有读优选单元结构和写驱动器的静态随机存取存储器（SRAM）。 在一个实施例中，SRAM具有六个晶体管位单元。 读优选位单元通过提供两个反相器来实现，每个反相器具有上拉晶体管，下拉晶体管和通过栅极晶体管。 每个上拉晶体管与反馈回路相关联。 反馈环路改善了随机的静态噪声容限。 每个晶体管具有宽度和长度。 传输栅晶体管的长度增加。 下拉晶体管的宽度彼此相等，并且也等于通过栅极晶体管的宽度。 通过栅极和下拉晶体管的宽度也可以相对于现有设计而增加。 也可以使用写辅助电路来提高性能。

    Flash memory cell with capacitive coupling between a metal floating gate and a metal control gate
    37.
    发明授权
    Flash memory cell with capacitive coupling between a metal floating gate and a metal control gate 有权
    具有金属浮动栅极和金属控制栅极之间的电容耦合的闪存单元

    公开(公告)号：US09047960B2

    公开(公告)日：2015-06-02

    申请号：US13957460

    申请日：2013-08-02

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Bin Yang ,  Zhongze Wang

    IPC: G11C16/00 ,  G11C16/10 ,  H01L21/28 ,  H01L29/66 ,  G11C16/14

    CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

    Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.

    Abstract translation: 一种装置包括存储晶体管。 存储晶体管包括被配置为存储电荷的浮动栅极和控制栅极。 浮动栅极通过电容耦合耦合到控制栅极。 浮动门和控制门是金属的。 该装置还包括耦合到存储晶体管的存取晶体管。 存取晶体管的栅极耦合到字线。 存储晶体管和存取晶体管串联耦合在位线和源极线之间。

    Parallel processing of a convolutional layer of a neural network with compute-in-memory array
    38.
    发明授权
    Parallel processing of a convolutional layer of a neural network with compute-in-memory array 有权

    公开(公告)号：US11562205B2

    公开(公告)日：2023-01-24

    申请号：US16576597

    申请日：2019-09-19

    Applicant: QUALCOMM Incorporated

    Inventor： Zhongze Wang ,  Ye Lu

    IPC: G06N3/04 ,  G06F7/544 ,  G06F17/15

    Abstract: An apparatus includes first and second compute-in-memory (CIM) arrays. The first CIM array is configured to store weights corresponding to a filter tensor, to receive a first set of activations corresponding to a first receptive field of an input, and to process the first set of activations with the weights to generate a corresponding first tensor of output values. The second CIM array is configured to store a first copy of the weights corresponding to the filter tensor and to receive a second set of activations corresponding to a second receptive field of the input. The second CIM array is also configured to process the second set of activations with the first copy of the weights to generate a corresponding second tensor of output values. The first and second compute-in-memory arrays are configured to process the first and second receptive fields in parallel.

    DIGITAL COMPUTE-IN-MEMORY (DCIM) BIT CELL CIRCUIT LAYOUTS AND DCIM ARRAYS FOR MULTIPLE OPERATIONS PER COLUMN
    40.
    发明申请
    DIGITAL COMPUTE-IN-MEMORY (DCIM) BIT CELL CIRCUIT LAYOUTS AND DCIM ARRAYS FOR MULTIPLE OPERATIONS PER COLUMN 有权

    公开(公告)号：US20220392524A1

    公开(公告)日：2022-12-08

    申请号：US17341797

    申请日：2021-06-08

    Applicant: QUALCOMM Incorporated

    Inventor： Xiaonan Chen ,  Zhongze Wang ,  Yandong Gao ,  Mustafa Badaroglu

    IPC: G11C11/419 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4091 ,  G06N3/063 ,  G06F7/544

    Abstract: Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM array circuits for multiple operations per column are disclosed. A DCIM bit cell array circuit including DCIM bit cell circuits comprising exemplary DCIM bit cell circuit layouts disposed in columns is configured to evaluate the results of multiple multiply operations per clock cycle. The DCIM bit cell circuits in the DCIM bit cell circuit layouts each couples to one of a plurality of column output lines in a column. In this regard, in each cycle of a system clock, each of the plurality of column output lines receives a result of a multiply operation of a DCIM bit cell circuit coupled to the column output line. The DCIM bit cell array circuit includes digital sense amplifiers coupled to each of the plurality of column output lines to reliably evaluate a result of a plurality of multiply operations per cycle.

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