公开(公告)号：US20240162095A1

公开(公告)日：2024-05-16

申请号：US18423648

申请日：2024-01-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Da Huang ,  Hao-Heng Liu ,  Li-Te Lin

IPC: H01L21/8234 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0207 ,  H01L27/088

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a gate electrode over a substrate. A pair of source/drain regions are disposed in the substrate on opposing sides of the gate electrode. A dielectric layer is over the substrate. An etch stop layer is between the gate electrode and the dielectric layer. A gate capping layer overlies the gate electrode, continuously extends from a top surface of the etch stop layer to a top surface of the gate electrode, and comprises a curved sidewall over the top surface of the etch stop layer. A conductive contact overlies an individual source/drain region. A width of the conductive contact continuously decreases from a top surface of the conductive contact to a first point disposed above a lower surface of the gate capping layer. The conductive contact extends along the curved sidewall of the gate capping layer.

公开(公告)号：US20240145313A1

公开(公告)日：2024-05-02

申请号：US18407020

申请日：2024-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyuk YIM ,  Kang Ill SEO

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823487 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827

Abstract: Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the Pt fin structures.

公开(公告)号：US20240136426A1

公开(公告)日：2024-04-25

申请号：US18481433

申请日：2023-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungheon Lee ,  Donghyun Roh ,  Jangho Lee

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device, includes forming a mask layer on a semiconductor structure having a plurality of gate lines and a plurality of intergate insulating portions, forming an opening that exposes a cut region of the plurality of gate lines in the mask layer, forming a separation hole by removing a portion of a gate capping layer exposed by the opening, forming a pyrolysis material pattern in the separation hole, forming an etch stop layer on an upper surface of the mask layer and on a side wall portion of the separation hole from which the pyrolysis material pattern is removed, while the pyrolysis material pattern is decomposed and removed, and removing a portion of the gate electrode exposed by the separation hole using the etch stop layer.

公开(公告)号：US20240113112A1

公开(公告)日：2024-04-04

申请号：US18526062

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ryan Chia-Jen Chen ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yu-Hsien Lin ,  Ming-Ching Chang ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Yi-Chun Chen

IPC: H01L27/088 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7842 ,  H01L21/3212

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

公开(公告)号：US11948973B2

公开(公告)日：2024-04-02

申请号：US17402985

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Huan-Chieh Su ,  Shi Ning Ju ,  Kuan-Ting Pan ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/0886 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

公开(公告)号：US11948936B2

公开(公告)日：2024-04-02

申请号：US18305556

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Wang ,  Chih Chieh Yeh ,  Zi-Ang Su ,  Chia-Ju Chou ,  Ming-Shuan Li

IPC: H01L27/02 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0266 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0296 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.

公开(公告)号：US20240105719A1

公开(公告)日：2024-03-28

申请号：US18524934

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

公开(公告)号：US20240098959A1

公开(公告)日：2024-03-21

申请号：US18517275

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Chia-Ta Yu ,  Cheng-Yu Yang ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H10B10/00 ,  H01L21/027 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66

CPC classification number: H10B10/12 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66636 ,  H10B10/18 ,  H01L29/165

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

公开(公告)号：US20240088145A1

公开(公告)日：2024-03-14

申请号：US18519263

申请日：2023-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Chih-Hao Wang ,  Kuo-Cheng Ching

IPC: H01L27/088 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

公开(公告)号：US20240088139A1

公开(公告)日：2024-03-14

申请号：US18516311

申请日：2023-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY , LTD.

Inventor： Meng-Han LIN ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823418 ,  H01L21/823437

Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.