公开(公告)号：US20170263475A1

公开(公告)日：2017-09-14

申请号：US15500213

申请日：2015-07-31

申请人： KATHOLIEKE UNIVERSITEIT LEUVEN

发明人： Jean-Pierre LOCQUET ,  Chen-Yi SU

IPC分类号： H01L21/67 ,  H01L21/02 ,  H01L21/687 ,  C23C14/58 ,  C23C16/56

CPC分类号： H01L21/67109 ,  C23C14/228 ,  C23C14/5806 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/02527 ,  H01L21/02529 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02689 ,  H01L21/68714

摘要： A heating device for heating the surface of a substrate. The heating device comprises a gas source comprising an inert material supply inert under the operating conditions of the heating device, the gas source being adapted for supplying a hot jet of a gas comprising at least elements of said inert material on the substrate. The gas source is adapted for heating the hot jet of the gas to a temperature above 1500° C.

公开(公告)号：US09728463B2

公开(公告)日：2017-08-08

申请号：US15209093

申请日：2016-07-13

申请人： Samsung Electronics Co., Ltd.

发明人： Ha-jin Lim ,  Gi-gwan Park ,  Sang-yub Ie ,  Jong-han Lee ,  Jeong-hyuk Yim ,  Hye-ri Hong

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/67

CPC分类号： H01L21/823462 ,  H01L21/02123 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/02348 ,  H01L21/02356 ,  H01L21/02362 ,  H01L21/28185 ,  H01L21/3003 ,  H01L21/67207 ,  H01L29/66795

摘要： Methods of manufacturing a semiconductor device are provided. The methods may include forming a fin-type active region protruding from a substrate and forming a gate insulating film covering a top surface and both sidewalls of the fin-type active region. The gate insulating film may include a high-k dielectric film. The methods may also include forming a metal-containing layer on the gate insulating film, forming a silicon capping layer containing hydrogen atoms on the metal-containing layer, removing a portion of the hydrogen atoms contained in the silicon capping layer, removing the silicon capping layer and at least a portion of the metal-containing layer, and forming a gate electrode on the gate insulating film. The gate electrode may cover the top surface and the both sidewalls of the fin-type active region.

公开(公告)号：US20170170011A1

公开(公告)日：2017-06-15

申请号：US15244875

申请日：2016-08-23

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： ERHU ZHENG ,  SHILIANG JI ,  YIYING ZHANG

IPC分类号： H01L21/02 ,  H01L29/788 ,  H01L21/3105 ,  H01L27/115 ,  H01L21/28

CPC分类号： H01L21/02285 ,  H01L21/02118 ,  H01L21/02343 ,  H01L21/02356 ,  H01L21/28273 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/76801 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76837 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/7887

摘要： A method for fabricating an NAND flash memory includes providing a semiconductor substrate with a core region and a peripheral region, forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a first dielectric layer. The method further includes forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, and forming a solid dielectric layer through a solidification treatment process performed on the flowable dielectric layer. Voids and seams formed in the top portion of the first dielectric layer are filled by the solid dielectric layer. The method also includes removing the solid dielectric layer and a portion of the first dielectric layer to expose a top portion of the gate stack structures, and forming a metal silicide layer on each gate stack structure.

公开(公告)号：US20170133477A1

公开(公告)日：2017-05-11

申请号：US15417464

申请日：2017-01-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Takashi ANDO ,  Aritra DASGUPTA ,  Oleg GLUSCHENKOV ,  Balaji KANNAN ,  Unoh KWON

IPC分类号： H01L29/51 ,  H01L21/8238 ,  H01L27/088

CPC分类号： H01L29/513 ,  H01L21/022 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/2636 ,  H01L21/268 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518

摘要： Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.

公开(公告)号：US09634124B2

公开(公告)日：2017-04-25

申请号：US14802902

申请日：2015-07-17

申请人： Intel Corporation

发明人： Sameer Pradhan ,  Jeanne Luce

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02

CPC分类号： H01L29/7851 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/76897 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

摘要： The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

公开(公告)号：US09627385B2

公开(公告)日：2017-04-18

申请号：US14839560

申请日：2015-08-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Guan-Lin Chen ,  Ting-Hung Hsu ,  Jiun-Jia Huang

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L27/0924 ,  H01L21/02356 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

摘要： A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.

公开(公告)号：US20170069531A1

公开(公告)日：2017-03-09

申请号：US15053383

申请日：2016-02-25

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hideki KANAI

IPC分类号： H01L21/768

CPC分类号： H01L21/76838 ,  H01L21/02356 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/467 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/76897

摘要： In one embodiment, a method of manufacturing a semiconductor device includes forming a convex portion including an interconnect and a first film above a substrate, forming a second film on the convex portion, and forming a concave portion having a first bottom face of the first film and a second bottom face lower than the upper face of the first film in the second film. The method further includes forming a polymer film in the concave portion by using a polymer that includes first and second portions respectively having first and second affinities for the first film, phase-separating the first and second portions to form a first pattern containing the first portion and located on the first bottom face and a second pattern containing the second portion and located on the second bottom face in the polymer film, and selectively removing the first or second pattern.

摘要翻译： 在一个实施例中，一种制造半导体器件的方法包括在基片上形成包括互连的凸部和第一膜，在凸部上形成第二膜，形成具有第一膜的第一底面的凹部 并且第二底面低于第二膜中的第一膜的上表面。 该方法还包括通过使用包含分别具有第一和第二亲和性的第一和第二部分的第一和第二部分的聚合物在该凹部中形成聚合物膜，相分离第一和第二部分以形成包含第一部分的第一图案 并且位于第一底面上，第二图案包含第二部分并且位于聚合物膜中的第二底面上，并且选择性地去除第一或第二图案。

公开(公告)号：US20170005006A1

公开(公告)日：2017-01-05

申请号：US14755829

申请日：2015-06-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Takashi ANDO ,  Aritra DASGUPTA ,  Oleg GLUSCHENKOV ,  Balaji KANNAN ,  Unoh KWON

IPC分类号： H01L21/8234 ,  H01L21/263 ,  H01L27/088 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/513 ,  H01L21/022 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/2636 ,  H01L21/268 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518

摘要： Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.

公开(公告)号：US20150206951A1

公开(公告)日：2015-07-23

申请号：US14158368

申请日：2014-01-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SU-HORNG LIN ,  LIN-JUNG WU

IPC分类号： H01L29/51 ,  H01L21/268 ,  H01L21/02 ,  H01L29/423 ,  H01L21/28 ,  H01L21/324

CPC分类号： H01L29/517 ,  H01L21/02345 ,  H01L21/02356 ,  H01L21/2686 ,  H01L21/28158 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/3105 ,  H01L21/324 ,  H01L29/42364 ,  H01L29/51

摘要： Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a substrate, a high k dielectric layer disposed over the substrate, and a gate layer over the high k dielectric layer. The high k dielectric layer is partially crystallized and comprising an average thickness of from about 10 Å to about 30 Å. Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The method includes (i) forming a high k dielectric layer with a thickness of from about 10 Å to about 30 Å over a substrate, (ii) forming a gate layer over the dielectric layer, and (iii) transforming at least a portion of the dielectric layer from a first phase to a second phase by microwave irradiation.

摘要翻译： 本公开的一些实施例提供半导体结构。 半导体结构包括衬底，设置在衬底上的高k电介质层，以及高k电介质层上的栅极层。 高k电介质层是部分结晶的，其平均厚度为约至约30埃。 本公开的一些实施例提供了一种用于制造半导体结构的方法。 该方法包括：（i）在衬底上形成厚度约为从大至大约30埃的高k电介质层，（ii）在电介质层上形成栅极层，和（iii）将至少一部分 通过微波照射从第一相到第二相的电介质层。

公开(公告)号：US20140370686A1

公开(公告)日：2014-12-18

申请号：US14474624

申请日：2014-09-02

申请人： Newport Fab, LLC dba Jazz Semiconductor

发明人： Paul D. Hurwitz ,  Robert L. Zwingman

IPC分类号： H01L21/764 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762

CPC分类号： H01L21/764 ,  H01L21/02356 ,  H01L21/306 ,  H01L21/76237 ,  H01L21/7624

摘要： Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.

摘要翻译： 公开了一种用于改善位于该结构的顶部半导体层中的相邻器件之间的电信号隔离的结构以及用于该结构制造的相关方法。 该结构包括延伸穿过顶部半导体层并通过顶部半导体层下面的基底氧化物层的沟槽的第一部分。 处理晶片位于基底氧化物层下方，并且具有倾斜侧壁的沟槽的第二部分延伸到处理晶片中。 倾斜的侧壁由植入物（例如氙或氩）非晶化，以减少处理晶片中的载流子迁移率并改善位于顶部半导体层中的相邻器件之间的电信号隔离。