知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

40 records (took 0.019 seconds)

    Epitaxial channel
    23.
    发明授权
    Epitaxial channel 有权
    外延通道

    公开(公告)号：US09525031B2

    公开(公告)日：2016-12-20

    申请号：US14208353

    申请日：2014-03-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Chia-Wen Liu ,  Yeh Hsu

    IPC: H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02

    CPC classification number: H01L29/165 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02535 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

    Abstract: Some embodiments of the present disclosure relate to an epitaxially grown replacement channel region within a transistor, which mitigates the variations within the channel of the transistor due to fluctuations in the manufacturing processes. The replacement channel region is formed by recessing source/drain and channel regions of the semiconductor substrate, and epitaxially growing a replacement channel region within the recess, which comprises epitaxially growing a lower epitaxial channel region over a bottom surface of the recess, and epitaxially growing an upper epitaxial channel region over a bottom surface of the recess. The lower epitaxial channel region retards dopant back diffusion from the upper epitaxial channel region, resulting in a steep retrograde dopant profile within the replacement channel region. The upper epitaxial channel region increases carrier mobility within the channel. The replacement channel region provides improved drive current, thereby enabling better performance and higher yield.

    Abstract translation: 本公开的一些实施例涉及晶体管内的外延生长的替换沟道区，其由于制造工艺的波动而减轻晶体管的沟道内的变化。 替换通道区域通过使半导体衬底的源极/漏极和沟道区域凹陷形成，并且在凹槽内外延生长置换沟道区域，其包括在凹部的底表面上外延生长下部外延沟道区域，并且外延生长 在所述凹部的底表面上方的上部外延沟道区域。 下部外延沟道区域从上部外延沟道区域延迟掺杂剂反向扩散，导致替代沟道区域内的陡峭的逆向掺杂物分布。 上部外延沟道区增加了沟道内的载流子迁移率。 替代通道区域提供改善的驱动电流，从而实现更好的性能和更高的产量。

    EPITAXIAL CHANNEL WITH A COUNTER-HALO IMPLANT TO IMPROVE ANALOG GAIN
    25.
    发明申请
    EPITAXIAL CHANNEL WITH A COUNTER-HALO IMPLANT TO IMPROVE ANALOG GAIN 有权
    外来通道与计数器植入物提高模拟增益

    公开(公告)号：US20160284800A1

    公开(公告)日：2016-09-29

    申请号：US15172417

    申请日：2016-06-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Yi-Ming Sheu

    IPC: H01L29/10 ,  H01L29/78 ,  H01L27/088

    CPC classification number: H01L29/1054 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833

    Abstract: The present disclosure relate to an integrated chip having long-channel and short-channel transistors having channel regions with different doping profiles. In some embodiments, the integrated chip includes a first gate electrode arranged over a first channel region having first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have a dopant profile, respectively along the first length and the second length, which has a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is also higher by the edges of the first channel region than by the edges of the second channel region.

    Abstract translation: 本公开涉及具有具有不同掺杂特性的沟道区的具有长沟道和短沟道晶体管的集成芯片。 在一些实施例中，集成芯片包括布置在具有第一长度的第一沟道区域上的第一栅极电极和布置在具有大于第一长度的第二长度的第二沟道区域上的第二栅电极。 第一沟道区域和第二沟道区域分别具有沿着第一长度和第二长度的掺杂剂分布，其掺杂浓度比边界高于第一沟道区和第二沟道区的中间。 掺杂剂浓度也比第一通道区域的边缘高于第二通道区域的边缘。

    Dislocation stress memorization technique (DSMT) on epitaxial channel devices
    26.
    发明授权
    Dislocation stress memorization technique (DSMT) on epitaxial channel devices 有权
    外延通道器件上的位错应力记忆技术（DSMT）

    公开(公告)号：US09419136B2

    公开(公告)日：2016-08-16

    申请号：US14252147

    申请日：2014-04-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

    CPC classification number: H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

    Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated method of formation. The transistor device has an epitaxial stack disposed over a semiconductor substrate, and a gate structure disposed over the epitaxial stack. A channel region extends below the gate structure between epitaxial source and drain regions located on opposing sides of the gate structure. First and second dislocation stress memorization (DSM) regions have a stressed lattice that generates stress within the channel region. The first and second DSM regions respectively extend from below the epitaxial source region to a first location within the epitaxial source region from below the epitaxial drain region to a second location within the epitaxial drain region. Using the first and second DSM regions to stress the channel region, improves device performance.

    Abstract translation: 本公开涉及具有外延源极和漏极区域的晶体管器件，其具有向外延沟道区域提供应力的位错应力存储（DSM）区域和相关联的形成方法。 晶体管器件具有设置在半导体衬底上的外延层，以及设置在外延层上的栅极结构。 沟道区域在位于栅极结构的相对侧的外延源极和漏极区域之间的栅极结构的下方延伸。 第一和第二位错应力记忆（DSM）区域具有在沟道区域内产生应力的应力晶格。 第一和第二DSM区域分别从外延源区域的下面延伸到外延源区域内的从外延漏极区域下方的第一位置到外延漏极区域内的第二位置。 使用第一和第二DSM区域来压缩通道区域，提高了设备​​性能。

    Transistor having replacement gate and epitaxially grown replacement channel region
    28.
    发明授权
    Transistor having replacement gate and epitaxially grown replacement channel region 有权
    晶体管具有替代栅极和外延生长的替换沟道区域

    公开(公告)号：US09236445B2

    公开(公告)日：2016-01-12

    申请号：US14156505

    申请日：2014-01-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Wen Liu ,  Tsung-Hsing Yu ,  Wei-Hao Wu ,  Meikei Ieong ,  Ken-Ichi Goto ,  Zhiqiang Wu

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/36

    CPC classification number: H01L29/66545 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

    Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.

    Abstract translation: 本公开提供了一种形成晶体管的方法。 在该方法中，在半导体衬底上形成虚拟栅极结构。 然后在半导体衬底中形成源极/漏极区，使得布置在半导体衬底中的伪栅极结构下方的沟道区彼此分离源极/漏极。 在形成源极/漏极区之后，去除伪栅极结构。 在虚拟栅极结构被去除之后，去除沟道区域的表面区域以形成沟道区域凹陷。 然后在沟道区域凹陷中外延生长替换沟道区。

    Semiconductor device and manufacturing method thereof
    30.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11569294B2

    公开(公告)日：2023-01-31

    申请号：US16924162

    申请日：2020-07-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mauricio Manfrini ,  Chung-Te Lin ,  Ken-Ichi Goto

    IPC: H01L27/22 ,  H01L29/423 ,  H01L23/528 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

    Abstract: A semiconductor device includes a semiconductor substrate and an interconnection region disposed on the semiconductor substrate. The interconnection region includes stacked metallization levels, a magnetic tunnel junction, and a transistor. The magnetic tunnel junction is formed on a first conductive pattern of a first metallization level of the stacked metallization levels. The transistor is formed on a second conductive pattern of a second metallization level of the stacked metallization levels. The transistor is a vertical gate-all-around transistor. A drain contact of the transistor is electrically connected to the magnetic tunnel junction by the first conductive pattern of the first metallization level. The second metallization level is closer to the semiconductor substrate than the first metallization level.

Patent Agency Ranking