公开(公告)号：US09184234B2

公开(公告)日：2015-11-10

申请号：US14156546

申请日：2014-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yuan Chen ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/36 ,  H01L29/16 ,  H01L29/165 ,  H01L21/02 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type.

Abstract translation: 本公开的一些实施例涉及形成在包含第一杂质类型的掺杂杂质的半导体衬底中的晶体管器件。 该晶体管器件包括由包括第一杂质类型的掺杂杂质的δ掺杂层构成的沟道，并且被配置为在沟道内产生峰值掺杂剂浓度。 通道还包括覆盖在δ掺杂层上的含碳材料层，并且被配置为防止掺杂剂从δ-掺杂层和半导体衬底的反向扩散。 通道还包括覆盖在含碳材料层上的衬底材料层，并且被配置为在通道的表面附近实现陡峭的逆向掺杂剂浓度分布。 在一些实施例中，反掺杂层位于配置成减少半导体衬底内的泄漏的δ掺杂层的下面，并且包括与第一杂质类型相反的第二杂质类型的掺杂杂质。

公开(公告)号：US09899475B2

公开(公告)日：2018-02-20

申请号：US15172417

申请日：2016-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Yi-Ming Sheu

IPC: H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/1054 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relate to an integrated chip having long-channel and short-channel transistors having channel regions with different doping profiles. In some embodiments, the integrated chip includes a first gate electrode arranged over a first channel region having first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have a dopant profile, respectively along the first length and the second length, which has a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is also higher by the edges of the first channel region than by the edges of the second channel region.

公开(公告)号：US20170054022A1

公开(公告)日：2017-02-23

申请号：US15345814

申请日：2016-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/167 ,  H01L29/417 ,  H01L21/265 ,  H01L29/16

CPC classification number: H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region.

Abstract translation: 本公开涉及具有外延源极和漏极区域的晶体管器件，其具有向沟道区域提供应力的位错应力记忆（DSM）区域。 在一些实施例中，晶体管器件具有布置在衬底内的外延源极区域。 外延漏极区域布置在衬底内并且通过沟道区域与外延源极区域分离。 具有被配置为在沟道区内产生应力的受应力晶格的第一DSM区从外延源区的下方延伸到外延源区内的位置。 具有被配置为在沟道区内产生应力的应力晶格的第二DSM区从外延漏极区的下方延伸到外延漏极区内的位置。

公开(公告)号：US09553150B2

公开(公告)日：2017-01-24

申请号：US14880469

申请日：2015-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yuan Chen ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/36 ,  H01L29/16 ,  H01L29/165 ,  H01L21/265 ,  H01L29/167 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type.

Abstract translation: 本公开的一些实施例涉及形成在包含第一杂质类型的掺杂杂质的半导体衬底中的晶体管器件。 该晶体管器件包括由包括第一杂质类型的掺杂杂质的δ掺杂层构成的沟道，并且被配置为在沟道内产生峰值掺杂剂浓度。 通道还包括覆盖在δ掺杂层上的含碳材料层，并且被配置为防止掺杂剂从δ-掺杂层和半导体衬底的反向扩散。 通道还包括覆盖在含碳材料层上的衬底材料层，并且被配置为在通道的表面附近实现陡峭的逆向掺杂剂浓度分布。 在一些实施例中，反掺杂层位于配置成减少半导体衬底内的泄漏的δ掺杂层的下面，并且包括与第一杂质类型相反的第二杂质类型的掺杂杂质。

公开(公告)号：US09502409B2

公开(公告)日：2016-11-22

申请号：US14624782

申请日：2015-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jon-Hsu Ho ,  Chih-Ching Wang ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Chih Chieh Yeh ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

公开(公告)号：US20160035832A1

公开(公告)日：2016-02-04

申请号：US14880469

申请日：2015-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yuan Chen ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/165 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/36 ,  H01L29/16

CPC classification number: H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type.

公开(公告)号：US20150200253A1

公开(公告)日：2015-07-16

申请号：US14156546

申请日：2014-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yuan Chen ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L29/167 ,  H01L29/16 ,  H01L29/165 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/36

CPC classification number: H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type.

Abstract translation: 本公开的一些实施例涉及形成在包含第一杂质类型的掺杂杂质的半导体衬底中的晶体管器件。 该晶体管器件包括由包括第一杂质类型的掺杂杂质的δ掺杂层构成的沟道，并且被配置为在沟道内产生峰值掺杂剂浓度。 通道还包括覆盖在δ掺杂层上的含碳材料层，并且被配置为防止掺杂剂从δ-掺杂层和半导体衬底的反向扩散。 通道还包括覆盖在含碳材料层上的衬底材料层，并且被配置为在通道的表面附近实现陡峭的逆向掺杂剂浓度分布。 在一些实施例中，反掺杂层位于配置成减少半导体衬底内的泄漏的δ掺杂层的下面，并且包括与第一杂质类型相反的第二杂质类型的掺杂杂质。

公开(公告)号：US09525031B2

公开(公告)日：2016-12-20

申请号：US14208353

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Chia-Wen Liu ,  Yeh Hsu

IPC: H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02

CPC classification number: H01L29/165 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02535 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

Abstract: Some embodiments of the present disclosure relate to an epitaxially grown replacement channel region within a transistor, which mitigates the variations within the channel of the transistor due to fluctuations in the manufacturing processes. The replacement channel region is formed by recessing source/drain and channel regions of the semiconductor substrate, and epitaxially growing a replacement channel region within the recess, which comprises epitaxially growing a lower epitaxial channel region over a bottom surface of the recess, and epitaxially growing an upper epitaxial channel region over a bottom surface of the recess. The lower epitaxial channel region retards dopant back diffusion from the upper epitaxial channel region, resulting in a steep retrograde dopant profile within the replacement channel region. The upper epitaxial channel region increases carrier mobility within the channel. The replacement channel region provides improved drive current, thereby enabling better performance and higher yield.

Abstract translation: 本公开的一些实施例涉及晶体管内的外延生长的替换沟道区，其由于制造工艺的波动而减轻晶体管的沟道内的变化。 替换通道区域通过使半导体衬底的源极/漏极和沟道区域凹陷形成，并且在凹槽内外延生长置换沟道区域，其包括在凹部的底表面上外延生长下部外延沟道区域，并且外延生长 在所述凹部的底表面上方的上部外延沟道区域。 下部外延沟道区域从上部外延沟道区域延迟掺杂剂反向扩散，导致替代沟道区域内的陡峭的逆向掺杂物分布。 上部外延沟道区增加了沟道内的载流子迁移率。 替代通道区域提供改善的驱动电流，从而实现更好的性能和更高的产量。

公开(公告)号：US09502559B2

公开(公告)日：2016-11-22

申请号：US14880392

申请日：2015-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to method of forming a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated device. The method forms a first dislocation stress memorization (DSM) region and a second DSM region having stressed lattices within a substrate. The substrate is selectively etched to form a source cavity and a drain cavity extending from an upper surface of the substrate to positions contacting the first DSM region and the second DSM region. An epitaxial source is formed within the source cavity and an epitaxial drain region is formed within the drain cavity. A gate structure is formed over the substrate at a location laterally between the epitaxial source region and the epitaxial drain region.

Abstract translation: 本公开涉及形成具有外延源极和漏极区域的晶体管器件的方法，该区域具有向外延沟道区域提供应力的位错应力存储（DSM）区域以及相关联的器件。 该方法形成第一位错应力记忆（DSM）区域和在衬底内具有受压晶格的第二DSM区域。 选择性地蚀刻衬底以形成从衬底的上表面延伸到与第一DSM区和第二DSM区接触的位置的源腔和漏腔。 在源极腔内形成外延源，在漏极腔内形成外延漏极区。 在外延源极区域和外延漏极区域之间的横向位置的衬底上形成栅极结构。

公开(公告)号：US20160284800A1

公开(公告)日：2016-09-29

申请号：US15172417

申请日：2016-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Yi-Ming Sheu

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/1054 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relate to an integrated chip having long-channel and short-channel transistors having channel regions with different doping profiles. In some embodiments, the integrated chip includes a first gate electrode arranged over a first channel region having first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have a dopant profile, respectively along the first length and the second length, which has a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is also higher by the edges of the first channel region than by the edges of the second channel region.

Abstract translation: 本公开涉及具有具有不同掺杂特性的沟道区的具有长沟道和短沟道晶体管的集成芯片。 在一些实施例中，集成芯片包括布置在具有第一长度的第一沟道区域上的第一栅极电极和布置在具有大于第一长度的第二长度的第二沟道区域上的第二栅电极。 第一沟道区域和第二沟道区域分别具有沿着第一长度和第二长度的掺杂剂分布，其掺杂浓度比边界高于第一沟道区和第二沟道区的中间。 掺杂剂浓度也比第一通道区域的边缘高于第二通道区域的边缘。