公开(公告)号：US20230369225A1

公开(公告)日：2023-11-16

申请号：US18357286

申请日：2023-07-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53276 ,  H01L21/76834 ,  H01L21/76802 ,  H01L23/5226 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/53295 ,  H01L21/76877 ,  H01L21/76805

摘要： A semiconductor structure is provided. The semiconductor structure includes a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ILD) layer. The semiconductor structure includes a first graphene layer disposed over the first conductive feature and a second graphene layer disposed over a portion of the second conductive feature. An etch-stop layer (ESL) is horizontally interposed between the first graphene layer and the second graphene layer. A side surface of the first or the second graphene layer directly contacts a side surface of the ESL. A third conductive feature is electrically coupled to the second conductive feature. The third conductive feature is separated from the first graphene layer by a portion of the ESL, and the third conductive feature also directly contacts a top surface of the ESL.

公开(公告)号：US11721627B2

公开(公告)日：2023-08-08

申请号：US17403267

申请日：2021-08-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/321

CPC分类号： H01L23/53276 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/3212 ,  H01L21/7684

摘要： A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

公开(公告)号：US11658092B2

公开(公告)日：2023-05-23

申请号：US17097441

申请日：2020-11-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Cherng-Shiaw Tsai ,  Ting-Ya Lo ,  Cheng-Chin Lee ,  Chi-Lin Teng ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/373 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L23/367

CPC分类号： H01L23/373 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/53295

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

公开(公告)号：US20230112282A1

公开(公告)日：2023-04-13

申请号：US18064561

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285

摘要： A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

公开(公告)号：US11527435B2

公开(公告)日：2022-12-13

申请号：US17443506

申请日：2021-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321

摘要： A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

公开(公告)号：US20220352019A1

公开(公告)日：2022-11-03

申请号：US17859981

申请日：2022-07-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Ping Chen ,  Ming-Han Lee ,  Shin-Yi Yang ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Shau-Lin Shue ,  Min Cao

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

公开(公告)号：US20220328351A1

公开(公告)日：2022-10-13

申请号：US17838723

申请日：2022-06-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Ping Chen ,  Shau-Lin Shue ,  Min Cao

IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/522

摘要： The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.

公开(公告)号：US20220165613A1

公开(公告)日：2022-05-26

申请号：US17671222

申请日：2022-02-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

摘要： Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

公开(公告)号：US20220115327A1

公开(公告)日：2022-04-14

申请号：US17556134

申请日：2021-12-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L21/324

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

公开(公告)号：US20220013403A1

公开(公告)日：2022-01-13

申请号：US16923424

申请日：2020-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532

摘要： The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.