公开(公告)号：US08923060B2

公开(公告)日：2014-12-30

申请号：US13721963

申请日：2012-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil Shim ,  Jaehoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  H01L27/115 ,  G11C16/34 ,  G11C16/30

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  H01L27/1157 ,  H01L27/11582

Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array including a plurality of memory cells; a word line driver configured to at least one of select and unselect a plurality of word lines connected with the plurality of memory cells, respectively, and to supply voltages to the plurality of word lines; and a read/write circuit configured to apply bias voltages to a plurality of bit lines connected with the plurality of memory cells. The read/write circuit may be configured to adjust levels of the bias voltages applied to the plurality of bit lines according to location of a selected word line among the plurality of word lines.

Abstract translation: 根据发明构思的示例实施例，非易失性存储器件包括包括多个存储器单元的存储单元阵列; 字线驱动器，被配置为分别选择和取消选择与所述多个存储器单元连接的多个字线中的至少一个，并向所述多个字线提供电压; 以及读/写电路，被配置为向与多个存储单元连接的多个位线施加偏置电压。 读/写电路可以被配置为根据多个字线中所选择的字线的位置来调整施加到多个位线的偏置电压的电平。

公开(公告)号：US20140357054A1

公开(公告)日：2014-12-04

申请号：US14458998

申请日：2014-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Sung-Min Hwang ,  Kihyun Hwang ,  Jaehoon Jang

IPC: H01L21/762 ,  H01L27/115

CPC classification number: H01L21/76254 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42348

Abstract: A semiconductor device can include a first substrate and conductive patterns on the first substrate, where the conductive patterns are disposed in stacks vertically extending from the substrate. An active pillar can be on the first substrate vertically extend from the first substrate throughthe conductive patterns to provide vertical string transistors on the first substrate. A second substrate can be on the conductive patterns and the active pillar opposite the first substrate. A peripheral circuit transistor can be on the second substrate opposite the first substrate, where the peripheral circuit transistor can be adjacent to and overlap an uppermost pattern of the conductive patterns.

Abstract translation: 半导体器件可以包括第一衬底和第一衬底上的导电图案，其中导电图案布置在从衬底垂直延伸的堆叠中。 活性柱可以在第一衬底上，从第一衬底垂直地延伸穿过导电图案，以在第一衬底上提供垂直串联晶体管。 第二基板可以位于与第一基板相对的导电图案和有源柱上。 外围电路晶体管可以在与第一衬底相对的第二衬底上，其中外围电路晶体管可以与导电图案的最上面的图案相邻并且与其重叠。

公开(公告)号：US20140248766A1

公开(公告)日：2014-09-04

申请号：US14276124

申请日：2014-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-JOO SHIM ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

IPC: H01L21/768

CPC classification number: H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract translation: 提供一种三维半导体器件及其制造方法。 三维半导体器件可以包括用于提供间隙区域的模具结构和包括设置在间隙区域中的多个互连图案的互连结构。 模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。

公开(公告)号：US20140092686A1

公开(公告)日：2014-04-03

申请号：US14095597

申请日：2013-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil Shim ,  Jaehun Jeong ,  Jaehoon Jang ,  Kihyun Kim

IPC: G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157

Abstract: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

Abstract translation: 非易失性存储器件利用垂直堆叠的非易失性存储器单元串（例如，NAND型串），其可选择性地耦合到衬底内的公共源极线。 该选择耦合可以由具有不同阈值电压的横向接地选择晶体管提供，这些阈值电压考虑了非垂直堆叠的非易失性存储单元串与公共源极线之间的不同横向间隔。

公开(公告)号：US11444094B2

公开(公告)日：2022-09-13

申请号：US16782737

申请日：2020-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sejun Park ,  Jaeduk Lee ,  Jaehoon Jang ,  Jin-Kyu Kang ,  Seungwan Hong ,  Okcheon Hong

IPC: H01L27/11582 ,  H01L27/11556 ,  G11C5/02

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

公开(公告)号：US10396088B2

公开(公告)日：2019-08-27

申请号：US15696276

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon Lee ,  Sunil Shim ,  Jaeduk Lee ,  Jaehoon Jang ,  Jeehoon Han

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.

公开(公告)号：US09401209B2

公开(公告)日：2016-07-26

申请号：US14826814

申请日：2015-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil Shim ,  Jang-Gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

IPC: H01L29/78 ,  G11C16/04 ,  H01L23/535 ,  H01L27/115

CPC classification number: G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

公开(公告)号：US09330770B2

公开(公告)日：2016-05-03

申请号：US14590665

申请日：2015-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil Shim ,  Jaehoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  H01L27/115

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US09117923B2

公开(公告)日：2015-08-25

申请号：US13830208

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil Shim ,  Jaehoon Jang ,  Hansoo Kim ,  Sungmin Hwang ,  Wonseok Cho ,  Jinsoo Lim

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L29/7926 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer, and forming a conductive pattern.

Abstract translation: 一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过第一多层结构形成第一孔，在第一孔中形成第一半导体图案 在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案 形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器 层，形成导电图案。

公开(公告)号：US08969162B2

公开(公告)日：2015-03-03

申请号：US13933772

申请日：2013-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

IPC: H01L21/336 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

Abstract translation: 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。