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    Semiconductor memory devices and methods of fabricating the same
    1.
    发明授权
    Semiconductor memory devices and methods of fabricating the same 有权

    公开(公告)号：US11374008B2

    公开(公告)日：2022-06-28

    申请号：US17035843

    申请日：2020-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong-Hoon Son

    IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

    Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction traversing the first direction, a gate electrode extending through the plurality of layers and including a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, and a data storing element electrically connected to the one of the semiconductor patterns. The data storing element includes a first electrode electrically connected to the one of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes.

    Methods of forming a semiconductor device
    3.
    发明授权
    Methods of forming a semiconductor device 有权
    形成半导体器件的方法

    公开(公告)号：US08980731B2

    公开(公告)日：2015-03-17

    申请号：US13724632

    申请日：2012-12-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Kim ,  Sunghae Lee ,  Hanvit Yang ,  Dongwoo Kim ,  Chaeho Kim ,  Daehyun Jang ,  Ju-Eun Kim ,  Yong-Hoon Son ,  Sangryol Yang ,  Myoungbum Lee ,  Kihyun Hwang

    IPC: H01L21/04 ,  H01L21/82 ,  H01L21/336 ,  H01L21/3205 ,  H01L29/76 ,  H01L29/792 ,  H01L27/115 ,  H01L29/66

    CPC classification number: H01L21/04 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    Abstract: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.

    Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层，以及形成穿透第一层和第二层的开口。 所述方法还可以包括在开口中形成第一半导体图案。 所述方法还可以包括在第一半导体图案上形成绝缘图案。 所述方法还可以包括在绝缘图案上形成第二半导体图案。 所述方法还可以包括在第一半导体图案中提供掺杂剂。 此外，所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。

    METHOD OF MANUFACTURING A VERTICAL-TYPE SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A VERTICAL-TYPE SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF MANUFACTURING A VERTICAL-TYPE SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A VERTICAL-TYPE SEMICONDUCTOR DEVICE 有权
    制造垂直型半导体器件的方法和操作垂直型半导体器件的方法

    公开(公告)号：US20130134501A1

    公开(公告)日：2013-05-30

    申请号：US13750066

    申请日：2013-01-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC: H01L29/78

    CPC classification number: H01L29/7827 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7841

    Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

    Abstract translation: 在垂直型半导体器件中，其制造方法及其操作方法，垂直型半导体器件包括：具有设置在基板上的柱状的单晶半导体图案， 单晶半导体图案，并且具有比单晶半导体图案的上表面低的上表面，形成在栅极的上表面上的掩模图案，所述掩模图案具有与单个半导体图案的上表面共面的上表面 晶体半导体图案，在单晶半导体图案下的衬底中的第一杂质区域和在单晶半导体图案的上表面下方的第二杂质区域。 形成在单晶半导体图案中的垂直型立柱晶体可以提供优异的电性能。 在第二杂质区域中的单晶半导体图案的上表面上没有设置掩模图案，从而减少处理的失败。

    Semiconductor memory device and method of manufacturing the same
    9.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权

    公开(公告)号：US11437380B2

    公开(公告)日：2022-09-06

    申请号：US16898640

    申请日：2020-06-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang-Ho Park ,  Jae Hoon Kim ,  Yong-Hoon Son ,  Seung Jae Jung

    IPC: H01L27/06 ,  H01L27/108 ,  H01L21/768

    Abstract: A semiconductor memory device including first-first conductive lines on a substrate; second-first conductive lines on the first-first conductive lines; first contacts connected to the first-first conductive lines; and second contacts connected to the second-first conductive lines, wherein the first-first conductive lines protrude in a first direction beyond the second-first conductive lines; the first-first conductive lines include first regions having a first thickness, second regions having a second thickness, the second thickness being greater than the first thickness, and third regions having a third thickness, the third thickness being smaller than the first thickness and smaller than the second thickness, and the second regions of the first-first conductive lines are between the first regions of the first-first conductive lines and the third regions of the first-first conductive lines.

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11348924B2

    公开(公告)日：2022-05-31

    申请号：US16923572

    申请日：2020-07-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae Hoon Kim ,  Kwang-Ho Park ,  Yong-Hoon Son ,  Hyunji Song ,  Gyeonghee Lee ,  Seungjae Jung

    IPC: G11C5/06 ,  H01L27/108 ,  G11C11/4097

    Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

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