公开(公告)号：US20220352084A1

公开(公告)日：2022-11-03

申请号：US17748308

申请日：2022-05-19

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Tao Cheng ,  Nan-Cheng Chen ,  Che-Ya Chou ,  Wen-Chou Wu ,  Yen-Ju Lu ,  Chih-Ming Hung ,  Wei-Hsiu Hsu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065 ,  H01L25/16 ,  H01L23/50 ,  H01L23/498 ,  H01L21/683 ,  H01Q9/04 ,  H01L23/66 ,  H01Q1/22

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US10199318B2

公开(公告)日：2019-02-05

申请号：US15481500

申请日：2017-04-07

Applicant: MEDIATEK INC.

Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Che-Hung Kuo ,  Che-Ya Chou ,  Wei-Che Huang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L25/10

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.

公开(公告)号：US10074628B2

公开(公告)日：2018-09-11

申请号：US15182613

申请日：2016-06-15

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih Liu ,  Che-Ya Chou

IPC: H01L23/495 ,  H01L25/065 ,  H01L21/78 ,  H01L25/00 ,  H01L25/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/03 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/16225 ,  H01L2924/00015

Abstract: A system-in-package (SiP) includes a RDL structure having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side of the RDL structure, wherein the first semiconductor die has an active surface that is in direct contact with the RDL structure; a plurality of conductive fingers on the first side of the RDL structure around the first semiconductor die; a second semiconductor die stacked directly on the first semiconductor die, wherein the second semiconductor die is electrically connected to the plurality of conductive fingers through a plurality of bond wires; and a mold cap encapsulating the first semiconductor die, the conductive fingers, the second semiconductor die, and the first side of the RDL structure.

公开(公告)号：US09818727B2

公开(公告)日：2017-11-14

申请号：US15012018

申请日：2016-02-01

Applicant: MediaTek Inc.

Inventor： Che-Hung Kuo ,  Ying-Chih Chen ,  Che-Ya Chou

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48265 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.

公开(公告)号：US20170243858A1

公开(公告)日：2017-08-24

申请号：US15588690

申请日：2017-05-07

Applicant: MEDIATEK INC.

Inventor： Che-Ya Chou ,  Kun-Ting Hung ,  Chia-Hao Yang ,  Nan-Cheng Chen

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/83005 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack disposed on the first surface of the carrier substrate. The chip stack includes a first semiconductor die, a second semiconductor die, and an interposer between the first semiconductor die and the second semiconductor die. The interposer transmits signals between the first semiconductor die and the second semiconductor die.

公开(公告)号：US09704808B2

公开(公告)日：2017-07-11

申请号：US15006082

申请日：2016-01-25

Applicant: MEDIATEK INC.

Inventor： Shih-Yi Syu ,  Tung-Hsien Hsieh ,  Che-Ya Chou

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H01L23/29 ,  H01L23/525

CPC classification number: H01L23/5386 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53228 ,  H01L23/5384 ,  H01L23/66 ,  H01L24/05 ,  H01L24/09 ,  H01L24/17 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/73209 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

公开(公告)号：US20160293575A1

公开(公告)日：2016-10-06

申请号：US15182613

申请日：2016-06-15

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih Liu ,  Che-Ya Chou

IPC: H01L25/065 ,  H01L25/16 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/16225 ,  H01L2924/00015

Abstract: A system-in-package (SiP) includes a RDL structure having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side of the RDL structure, wherein the first semiconductor die has an active surface that is in direct contact with the RDL structure; a plurality of conductive fingers on the first side of the RDL structure around the first semiconductor die; a second semiconductor die stacked directly on the first semiconductor die, wherein the second semiconductor die is electrically connected to the plurality of conductive fingers through a plurality of bond wires; and a mold cap encapsulating the first semiconductor die, the conductive fingers, the second semiconductor die, and the first side of the RDL structure.

Abstract translation: 系统级封装（SiP）包括具有第一侧和与第一侧相对的第二侧的RDL结构; 安装在所述RDL结构的第一侧上的第一半导体管芯，其中所述第一半导体管芯具有与所述RDL结构直接接触的有源表面; 在所述第一半导体管芯周围的所述RDL结构的第一侧上的多个导电指状物; 直接堆叠在第一半导体管芯上的第二半导体管芯，其中第二半导体管芯通过多个接合线电连接到多个导电指状物; 以及封装第一半导体管芯，导电指状物，第二半导体管芯和RDL结构的第一侧的模具盖。

公开(公告)号：US20150249060A1

公开(公告)日：2015-09-03

申请号：US14714331

申请日：2015-05-17

Applicant: Mediatek Inc.

Inventor： Thomas Matthew Gregorich ,  Tzu-Hung Lin ,  Che-Ya Chou

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05552

Abstract: A flip chip package includes: a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein part of the copper column overhangs the via opening.

Abstract translation: 倒装芯片封装包括：耦合到管芯的载体。 载体包括：用于将载体的表面耦合到载体中的电迹线的至少一个通孔; 以及至少一个电耦合到所述通孔的捕获垫，其中所述捕获垫被电镀在所述通孔上。 模具包括：至少形成在模具表面上的接合焊盘; 以及形成在所述接合焊盘上的至少一个铜柱，用于将所述管芯耦合到所述载体上的捕获垫，其中所述铜柱的一部分突出于所述通孔开口。

公开(公告)号：US11721882B2

公开(公告)日：2023-08-08

申请号：US17075561

申请日：2020-10-20

Applicant: MediaTek Inc.

Inventor： Fu-Yi Han ,  Che-Ya Chou ,  Che-Hung Kuo ,  Wen-Chou Wu ,  Nan-Cheng Chen ,  Min-Chen Lin ,  Hsing-Chih Liu

IPC: H01Q1/22 ,  H01L23/66 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01Q1/2283 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/16 ,  H01L24/20 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16141 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19042 ,  H01L2924/19106

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

公开(公告)号：US20210193540A1

公开(公告)日：2021-06-24

申请号：US17190584

申请日：2021-03-03

Applicant: MediaTek Inc.

Inventor： Nan-Cheng Chen ,  Che-Ya Chou ,  Hsing-Chih Liu ,  Che-Hung Kuo

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/482 ,  H01L25/04

Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.