公开(公告)号：US06010953A

公开(公告)日：2000-01-04

申请号：US886707

申请日：1997-07-01

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/10852 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S438/947

Abstract: A removable oxide spacer is used to reduce the size of a contact opening in a memory cell between polysilicon word lines below a lithographic minimum. The removable spacer is deposited before the buried contact patterning and etching. Since word lines diverge at a cell location, the removable spacer retains a lesser thickness over the divergent area contact opening and a greater thickness elsewhere between word lines due to the more narrow gap therebetween and the spacer being deposited such that it fills the gap. The removable spacer reduces the buried contact size since the actual self-aligned contact area is defined by the spacer sidewall. The removable spacer is formed of materials having higher etching selectivity relative to materials forming underlying structures. Etching of the spacer creates a buried contact opening smaller than a lithographic minimum because silicon oxide surrounding the buried contact area is protected by the removable spacer. The removable spacer is removed after the resist strip, leaving a sublithographic buried contact opening.

Abstract translation: 使用可去除的氧化物间隔物来减小低于光刻最小值的多晶硅字线之间的存储单元中的接触开口的尺寸。 可去除的间隔物在掩埋接触图案化和蚀刻之前被沉积。 由于字线在单元位置发散，所以可拆卸的间隔物在发散区域接触开口之间保持较小的厚度，并且由于其间较窄的间隙而间隔较大，并且间隔物被沉积以使其填充该间隙，因此在字线之间的其他位置具有更大的厚度。 由于实际的自对准接触区域由间隔壁侧壁限定，所以可拆卸间隔物减小了埋入接触尺寸。 可移除的间隔物由相对于形成底层结构的材料具有较高蚀刻选择性的材料形成。 间隔物的蚀刻产生小于光刻最小值的掩埋接触开口，因为围绕埋入接触区域的氧化硅被可移除间隔物保护。 在抗蚀剂条之后去除可移除的间隔物，留下亚光刻掩埋的接触开口。

公开(公告)号：US09058857B2

公开(公告)日：2015-06-16

申请号：US13269717

申请日：2011-10-10

Applicant: Zengtao T. Liu ,  Kirk D. Prall

Inventor： Zengtao T. Liu ,  Kirk D. Prall

IPC: G11C11/21 ,  G11C8/08 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C8/08 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0038 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2013/0083 ,  G11C2213/77

Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

Abstract translation: 本文描述的设备和方法可以操作以测量所选择的接入线路和与存储器阵列的多个存储器单元的选定单元相关联的选择的感测线之间的电压差。 可以将电压差与为存储器操作指定的参考电压进行比较。 可以响应于比较来调整施加到用于存储器操作的所选单元的选择电压，例如动态地补偿寄生电压降。

公开(公告)号：US20130121056A1

公开(公告)日：2013-05-16

申请号：US13293353

申请日：2011-11-10

Applicant: Zengtao T. Liu ,  Kirk D. Prall ,  Mike Violette

Inventor： Zengtao T. Liu ,  Kirk D. Prall ,  Mike Violette

IPC: G11C11/00 ,  H01L21/8239

CPC classification number: H01L27/2436 ,  G11C5/063 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/222 ,  H01L27/228 ,  H01L27/24 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/10 ,  H01L45/065 ,  H01L45/085 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147

Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

Abstract translation: 本公开包括包括电阻性存储器的方法和装置。 多个实施例包括耦合到数据线并包括第一电阻存储元件和第一存取器件的第一存储器单元，耦合到数据线并包括第二电阻存储元件和第二存取器件的第二存储单元， 形成在第一存取装置和第二存取装置之间的隔离装置，耦合到第一电阻存储元件的第一选择线和耦合到第二电阻存储元件的第二选择线，其中第二选择线与第一选择线分开 线。

公开(公告)号：US20130069030A1

公开(公告)日：2013-03-21

申请号：US13234875

申请日：2011-09-16

Applicant: David H. Wells ,  D.V. Nirmal Ramaswamy ,  Kirk D. Prall

Inventor： David H. Wells ,  D.V. Nirmal Ramaswamy ,  Kirk D. Prall

IPC: H01L45/00 ,  H01L21/8239

CPC classification number: H01L45/085 ,  G11C2213/73 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146

Abstract: Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode.

Abstract translation: 包括集成选择装置和存储元件的电阻式存储单元及其形成方法在此描述。 作为示例，电阻式存储单元可以包括包括肖特基接口的选择器件结构和与选择器件结构集成的存储元件，使得对应于肖特基界面的电极用作存储元件的第一电极。 存储元件可以包括形成在第一电极和第二电极之间的存储材料。

公开(公告)号：US20130010526A1

公开(公告)日：2013-01-10

申请号：US13618860

申请日：2012-09-14

Applicant: Durai Vishak Nirmal Ramaswamy ,  Kirk D. Prall

Inventor： Durai Vishak Nirmal Ramaswamy ,  Kirk D. Prall

IPC: G11C11/00 ,  H01L45/00

CPC classification number: H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147

Abstract: Some embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to a memory element. The electrode can include different materials located at different portions of the electrode. The materials can create different dielectrics contacting the memory elements at different locations. Various states of the materials in the memory device can be used to represent stored information. Other embodiments are described.

Abstract translation: 一些实施例包括存储器件及其形成方法。 存储器件可以包括耦合到存储元件的电极。 电极可以包括位于电极的不同部分的不同材料。 这些材料可以在不同位置产生接触存储元件的不同电介质。 可以使用存储器件中的材料的各种状态来表示存储的信息。 描述其他实施例。

公开(公告)号：US07956402B2

公开(公告)日：2011-06-07

申请号：US11970843

申请日：2008-01-11

Applicant: Chun Chen ,  Kirk D. Prall

Inventor： Chun Chen ,  Kirk D. Prall

IPC: H01L29/788

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7883

Abstract: The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.

Abstract translation: 本发明提供一种在半导体存储元件中形成双掺杂多晶硅浮动栅极的方法和装置。 该方法包括在半导体衬底上形成第一介电层并在第一介电层上形成浮置栅极，浮置栅极包括掺杂有第一类掺杂剂材料的第一层和掺杂有第二类掺杂剂的第二层 与第一层中的第一种掺杂剂材料相反的材料。 该方法还包括在浮置栅极上形成第二电介质层，在第二电介质层上形成控制栅极，以及在衬底中形成源极和漏极。

公开(公告)号：US07955935B2

公开(公告)日：2011-06-07

申请号：US11513933

申请日：2006-08-31

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L29/42332

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.

Abstract translation: 一种制造存储单元的方法，包括在第一介电层上形成纳米点并在纳米点上形成隔间电介质层，其中隔间电介质层封装在纳米点上。 为了形成存储器单元的侧壁，隔离介电层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对栅极间电介质层选择性的蚀刻来去除间隔栅电介质层和纳米点的剩余部分。

公开(公告)号：US07881113B2

公开(公告)日：2011-02-01

申请号：US11703487

申请日：2007-02-07

Applicant: Lyle D. Jones ,  Roger W. Lindsay ,  Kirk D. Prall

Inventor： Lyle D. Jones ,  Roger W. Lindsay ,  Kirk D. Prall

IPC: G11C16/04

CPC classification number: H01L27/115 ,  G11C5/02 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11524

Abstract: A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to the first active area string and to the second active area string. The relaxed metal pitch architecture may be applied to a non-volatile memory structure.

Abstract translation: 轻松的金属间距结构可以包括位线和第一有效区域串和第二有效区域串。 位线可以直接耦合到第一有效区域串和第二有效区域串。 轻松的金属间距结构可以应用于非易失性存储器结构。

公开(公告)号：US20100213458A1

公开(公告)日：2010-08-26

申请号：US12390703

申请日：2009-02-23

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L29/12 ,  H01L21/34

CPC classification number: H01L27/12 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/8221 ,  H01L27/10873 ,  H01L27/11514 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11597 ,  H01L27/1225 ,  H01L29/66825 ,  H01L29/7869 ,  H01L29/7881

Abstract: Rigid semiconductor memory using amorphous metal oxide semiconductor channels are useful in the production of thin-film transistor memory devices. Such devices include single-layer and multi-layer memory arrays of volatile or non-volatile memory cells. The memory cells can be formed to have a gate stack overlying an amorphous metal oxide semiconductor, with amorphous metal oxide semiconductor channels.

Abstract translation: 使用非晶金属氧化物半导体通道的刚性半导体存储器可用于制造薄膜晶体管存储器件。 这样的设备包括易失性或非易失性存储单元的单层和多层存储器阵列。 存储单元可以形成为具有覆盖在非晶金属氧化物半导体上的栅极堆叠，具有无定形金属氧化物半导体沟道。

公开(公告)号：US07279740B2

公开(公告)日：2007-10-09

申请号：US11127618

申请日：2005-05-12

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

Abstract translation: 描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的浮动栅极存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和用电子和空穴擦除，同时保持 高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。 直接隧道编程和擦除功能可以减少高能量载体对栅极堆叠和晶格的损害，减少写入疲劳和泄漏问题，并增强器件寿命。 本发明的存储器单元还允许在单个存储器单元中进行多位存储，并允许以降低的电压进行编程和擦除。 还提供了正电压擦除处理通孔隧穿。