公开(公告)号：US07279740B2

公开(公告)日：2007-10-09

申请号：US11127618

申请日：2005-05-12

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

Abstract translation: 描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的浮动栅极存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和用电子和空穴擦除，同时保持 高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。 直接隧道编程和擦除功能可以减少高能量载体对栅极堆叠和晶格的损害，减少写入疲劳和泄漏问题，并增强器件寿命。 本发明的存储器单元还允许在单个存储器单元中进行多位存储，并允许以降低的电压进行编程和擦除。 还提供了正电压擦除处理通孔隧穿。

公开(公告)号：US08063436B2

公开(公告)日：2011-11-22

申请号：US12829904

申请日：2010-07-02

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material.

Abstract translation: 存储单元包括控制栅极，电荷捕获材料和控制栅极与电荷捕获材料之间的电荷阻挡材料。 电荷阻挡材料被配置为允许通过从控制栅极到电荷捕获材料的孔的增强的F-N隧穿来擦除存储器单元。

公开(公告)号：US20100264482A1

公开(公告)日：2010-10-21

申请号：US12829904

申请日：2010-07-02

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material.

Abstract translation: 存储单元包括控制栅极，电荷捕获材料和控制栅极与电荷捕获材料之间的电荷阻挡材料。 电荷阻挡材料被配置为允许通过从控制栅极到电荷捕获材料的孔的增强的F-N隧穿来擦除存储器单元。

公开(公告)号：US07749848B2

公开(公告)日：2010-07-06

申请号：US11900595

申请日：2007-09-12

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L21/336

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

Abstract translation: 描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的浮动栅极存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和用电子和空穴擦除，同时保持 高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。 直接隧道编程和擦除功能可以减少高能量载体对栅极堆叠和晶格的损害，减少写入疲劳和泄漏问题，并增强器件寿命。 本发明的存储器单元还允许在单个存储器单元中进行多位存储，并允许以降低的电压进行编程和擦除。 还提供了正电压擦除处理通孔隧穿。

公开(公告)号：US08507341B2

公开(公告)日：2013-08-13

申请号：US13445797

申请日：2012-04-12

Applicant: Luan C. Tran ,  John Lee ,  Zengtao “Tony” Liu ,  Eric Freeman ,  Russell Nielsen

Inventor： Luan C. Tran ,  John Lee ,  Zengtao “Tony” Liu ,  Eric Freeman ,  Russell Nielsen

IPC: H01L21/8242

CPC classification number: H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

公开(公告)号：US20130113061A1

公开(公告)日：2013-05-09

申请号：US13290733

申请日：2011-11-07

Applicant: Chih-Yu Lai ,  Yeur-Luen Tu ,  Chih-Hui Huang ,  Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Luan C. Tran

Inventor： Chih-Yu Lai ,  Yeur-Luen Tu ,  Chih-Hui Huang ,  Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Luan C. Tran

IPC: H01L27/146 ,  H01L31/18 ,  H01L31/0232

CPC classification number: H01L27/1463 ,  H01L21/02129 ,  H01L21/223 ,  H01L21/2255 ,  H01L21/76224 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L31/09

Abstract: Provided is a semiconductor image sensor device. The image sensor device includes a substrate. The image sensor device includes a first pixel and a second pixel disposed in the substrate. The first and second pixels are neighboring pixels. The image sensor device includes an isolation structure disposed in the substrate and between the first and second pixels. The image sensor device includes a doped isolation device disposed in the substrate and between the first and second pixels. The doped isolation device surrounds the isolation structure in a conformal manner.

公开(公告)号：US20120193777A1

公开(公告)日：2012-08-02

申请号：US13445797

申请日：2012-04-12

Applicant: Luan C. Tran ,  John Lee ,  Zengtao "Tony" Liu ,  Eric Freeman ,  Russell Nielsen

Inventor： Luan C. Tran ,  John Lee ,  Zengtao "Tony" Liu ,  Eric Freeman ,  Russell Nielsen

IPC: H01L23/52

CPC classification number: H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract translation: 用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法在第一光致抗蚀剂层中限定多个特征。 该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。 下掩蔽层中的特征包括环形端。 该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。 该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。 沟槽具有沟槽宽度。

公开(公告)号：US20110285029A1

公开(公告)日：2011-11-24

申请号：US13194558

申请日：2011-07-29

Applicant: Luan C. Tran

Inventor： Luan C. Tran

IPC: H01L23/48 ,  B82Y99/00

CPC classification number: H01L21/76802 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L27/108 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Abstract translation: 制造具有与有源区域特征对准的紧密节距触点的半导体结构的方法，并且使用用于限定具有亚光刻尺寸的图案的各种技术同时制造自对准的紧密节距触点和导线。 还公开了具有与有源区域特征对准的紧密节距触点的半导体结构以及可选地对齐的导线，半导体结构具有紧密的节距接触孔和用于导线的对准的沟槽。

公开(公告)号：US20100289070A1

公开(公告)日：2010-11-18

申请号：US12845167

申请日：2010-07-28

Applicant: Luan C. Tran

Inventor： Luan C. Tran

IPC: H01L27/088 ,  H01L29/788 ,  H01L29/06

CPC classification number: H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28273 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

Abstract translation: 半导体材料的连续环路的不同部分彼此电隔离。 在一些实施例中，环路的端部与环路的中间部分电隔离。 在一些实施例中，具有在其端部连接在一起的两个腿的半导体材料的环通过间距倍增过程形成，其中间隔物的环形成在心轴的侧壁上。 去除心轴并且将一块掩模材料覆盖在间隔环的至少一端上。 在一些实施例中，掩模材料块覆盖间隔环的每一端。 由间隔物和块限定的图案被转移到半导体材料层。 这些块将所有环路电连接在一起。 沿循环的每条腿形成选择门。 这些块作为源/排水沟。 选择门被偏置在关闭状态以防止电流从环路的中部流向块，从而将中间部分与环的端部电隔离，并且还将环的不同的腿与每个 其他。

公开(公告)号：US07518184B2

公开(公告)日：2009-04-14

申请号：US11474362

申请日：2006-06-26

Applicant: Luan C. Tran

Inventor： Luan C. Tran

IPC: H01L29/76

CPC classification number: H01L27/10876 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10891 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7835

Abstract: Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

Abstract translation: 公开了自对准凹陷门结构和形成方法。 首先在半导体衬底中形成用于隔离的场氧化物区域。 多个列限定在形成在半导体衬底上的绝缘层中，接着在半导体衬底的暴露区域上形成薄的牺牲氧化物层，但不在场氧化物区域上。 然后在每列的侧壁和牺牲氧化物层和场氧化物区域的部分上方提供电介质材料。 进行第一蚀刻以在半导体衬底内形成第一组沟槽和在场氧化物区域内形成多个凹陷。 进行第二蚀刻以去除残留在柱的侧壁上的电介质残余物并形成第二组沟槽。 然后将多晶硅沉积在第二组沟槽内并在凹槽内形成凹陷的导电栅极。