Invention Grant
US08063436B2 Memory cells configured to allow for erasure by enhanced F-N tunneling of holes from a control gate to a charge trapping material
有权
存储单元被配置为允许通过增强的F-N隧穿从控制门到电荷捕获材料的擦除来擦除
- Patent Title: Memory cells configured to allow for erasure by enhanced F-N tunneling of holes from a control gate to a charge trapping material
- Patent Title (中): 存储单元被配置为允许通过增强的F-N隧穿从控制门到电荷捕获材料的擦除来擦除
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Application No.: US12829904Application Date: 2010-07-02
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Publication No.: US08063436B2Publication Date: 2011-11-22
- Inventor: Arup Bhattacharyya , Kirk D. Prall , Luan C. Tran
- Applicant: Arup Bhattacharyya , Kirk D. Prall , Luan C. Tran
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: H01L29/792
- IPC: H01L29/792
Abstract:
Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material.
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