公开(公告)号：US08063436B2

公开(公告)日：2011-11-22

申请号：US12829904

申请日：2010-07-02

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material.

Abstract translation: 存储单元包括控制栅极，电荷捕获材料和控制栅极与电荷捕获材料之间的电荷阻挡材料。 电荷阻挡材料被配置为允许通过从控制栅极到电荷捕获材料的孔的增强的F-N隧穿来擦除存储器单元。

公开(公告)号：US07279740B2

公开(公告)日：2007-10-09

申请号：US11127618

申请日：2005-05-12

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

Abstract translation: 描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的浮动栅极存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和用电子和空穴擦除，同时保持 高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。 直接隧道编程和擦除功能可以减少高能量载体对栅极堆叠和晶格的损害，减少写入疲劳和泄漏问题，并增强器件寿命。 本发明的存储器单元还允许在单个存储器单元中进行多位存储，并允许以降低的电压进行编程和擦除。 还提供了正电压擦除处理通孔隧穿。

公开(公告)号：US20100264482A1

公开(公告)日：2010-10-21

申请号：US12829904

申请日：2010-07-02

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material.

Abstract translation: 存储单元包括控制栅极，电荷捕获材料和控制栅极与电荷捕获材料之间的电荷阻挡材料。 电荷阻挡材料被配置为允许通过从控制栅极到电荷捕获材料的孔的增强的F-N隧穿来擦除存储器单元。

公开(公告)号：US07749848B2

公开(公告)日：2010-07-06

申请号：US11900595

申请日：2007-09-12

Applicant: Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

Inventor： Arup Bhattacharyya ,  Kirk D. Prall ,  Luan C. Tran

IPC: H01L21/336

CPC classification number: H01L29/792 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513

Abstract: Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

Abstract translation: 描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的浮动栅极存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和用电子和空穴擦除，同时保持 高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。 直接隧道编程和擦除功能可以减少高能量载体对栅极堆叠和晶格的损害，减少写入疲劳和泄漏问题，并增强器件寿命。 本发明的存储器单元还允许在单个存储器单元中进行多位存储，并允许以降低的电压进行编程和擦除。 还提供了正电压擦除处理通孔隧穿。

公开(公告)号：US08802526B2

公开(公告)日：2014-08-12

申请号：US13409832

申请日：2012-03-01

Applicant: Arup Bhattacharyya

Inventor： Arup Bhattacharyya

IPC: H01L21/336

CPC classification number: H01L29/513 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  Y10S438/954

Abstract: Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

Abstract translation: 描述了形成非易失性存储单元结构的方法，其有助于在反向和正常模式浮动节点存储器单元中使用具有不对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和擦除，同时保持高电荷阻挡屏障 和深载体捕获位点保持良好的电荷。 低电压直接隧道编程和擦除能力降低了高能量载流子对栅极堆叠和晶格的损害，减少了写入疲劳和增强了器件寿命。 低电压直接隧道编程和擦除功能还可以通过低电压设计和进一步的器件特性缩放来缩小尺寸。 这样的存储器单元还允许多个位存储。 这些特性允许这样的存储器单元在通用存储器的定义内操作，能够替换系统中的DRAM和ROM。

公开(公告)号：US08557672B2

公开(公告)日：2013-10-15

申请号：US13368206

申请日：2012-02-07

Applicant: Leonard Forbes ,  Kie Y. Ahn ,  Arup Bhattacharyya

Inventor： Leonard Forbes ,  Kie Y. Ahn ,  Arup Bhattacharyya

IPC: H01L21/20

CPC classification number: H01L21/02183 ,  C23C16/308 ,  C23C16/45525 ,  H01L21/02178 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31616 ,  H01L21/31637 ,  H01L28/60 ,  H01L28/65 ,  H01L29/518 ,  H01L29/7881

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.

公开(公告)号：US08530951B2

公开(公告)日：2013-09-10

申请号：US13608483

申请日：2012-09-10

Applicant: Arup Bhattacharyya

Inventor： Arup Bhattacharyya

IPC: H01L29/76 ,  G11C16/04

CPC classification number: H01L29/792 ,  B82Y10/00 ,  G11C16/10 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/513

Abstract: A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.

Abstract translation: 多功能和多层存储单元包括在衬底上形成的隧道层。 在一个实施例中，隧道层包括两层，例如HfO 2和LaAlO 3。 在隧道层上形成电荷阻挡层。 在一个实施方案中，该层由HfSiON形成。 控制栅极形成在电荷阻挡层上。 离散的捕获层嵌入在隧道层或电荷阻挡层中，这取决于期望的非挥发性水平。 离散捕获层越靠近衬底/绝缘体界面，器件的非易失性越低。 离散捕获层由具有均匀尺寸和分布的纳米晶体形成。

公开(公告)号：US08462557B2

公开(公告)日：2013-06-11

申请号：US12941458

申请日：2010-11-08

Applicant: Arup Bhattacharyya

Inventor： Arup Bhattacharyya

IPC: G11C11/34

CPC classification number: H01L29/792 ,  G11C16/0475 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/42336 ,  H01L29/513 ,  H01L29/7881

Abstract: Methods of operating dual-gate memory cells having asymmetric band-gap tunnel insulators using direct tunneling. The asymmetric band-gap tunnel insulators allow for low voltage direct tunneling programming and efficient erase with holes and/or electrons, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.

Abstract translation: 使用直接隧道操作具有非对称带隙隧道绝缘体的双栅极存储单元的方法。 非对称带隙隧道绝缘子允许低电压直接隧道编程和有空和/或电子的有效擦除，同时保持高电荷阻挡屏障和深载流子捕获位点以获得良好的电荷保留。

公开(公告)号：US08399332B2

公开(公告)日：2013-03-19

申请号：US13430098

申请日：2012-03-26

Applicant: Arup Bhattacharyya

Inventor： Arup Bhattacharyya

IPC: H01L21/20 ,  H01L21/02

CPC classification number: H01L21/3141 ,  H01G4/08 ,  H01L21/28194 ,  H01L21/316 ,  H01L28/40 ,  H01L29/513 ,  H01L29/517

Abstract: Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

公开(公告)号：US20130003456A1

公开(公告)日：2013-01-03

申请号：US13608483

申请日：2012-09-10

Applicant: Arup Bhattacharyya

Inventor： Arup Bhattacharyya

IPC: G11C16/10

CPC classification number: H01L29/792 ,  B82Y10/00 ,  G11C16/10 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/513

Abstract: A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.

Abstract translation: 多功能和多层存储单元包括在衬底上形成的隧道层。 在一个实施例中，隧道层包括两层，例如HfO 2和LaAlO 3。 在隧道层上形成电荷阻挡层。 在一个实施方案中，该层由HfSiON形成。 控制栅极形成在电荷阻挡层上。 离散的捕获层嵌入在隧道层或电荷阻挡层中，这取决于期望的非挥发性水平。 离散捕获层越靠近衬底/绝缘体界面，器件的非易失性越低。 离散捕获层由具有均匀尺寸和分布的纳米晶体形成。