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    NAND memory arrays
    1.
    发明授权
    NAND memory arrays 有权
    NAND存储器阵列

    公开(公告)号：US07482630B2

    公开(公告)日：2009-01-27

    申请号：US11209301

    申请日：2005-08-23

    Applicant: Roger W Lindsay

    Inventor： Roger W Lindsay

    IPC: H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC classification number: H01L27/11521 ,  H01L21/76897 ,  H01L27/115

    Abstract: A NAND memory array has a substrate, a source select gate formed on the substrate, and a drain select gate formed on the substrate. A string of floating-gate memory cells is formed on the substrate and is connected in series between the source select gate and the drain select gate. A drain contact has a head connected substantially perpendicularly to a stem. The head is aligned with the drain select gate and overlies a dielectric layer formed on the drain select gate. The stem overlies a polysilicon plug formed on the substrate. A bit line contact is in direct electrical contact with the head.

    Abstract translation: NAND存储器阵列具有衬底，形成在衬底上的源极选择栅极和形成在衬底上的漏极选择栅极。 在衬底上形成一串浮栅存储单元，并串联连接在源选择栅极和漏极选择栅极之间。 漏极接触头具有基本垂直于杆的连接头。 磁头与漏极选择栅极对准，并覆盖形成在漏极选择栅极上的电介质层。 茎覆盖形成在基底上的多晶硅塞。 位线接触器与头部直接电接触。

    Source lines for NAND memory devices
    2.
    发明授权
    Source lines for NAND memory devices 有权
    NAND存储器件的源极线

    公开(公告)号：US07202129B2

    公开(公告)日：2007-04-10

    申请号：US11247043

    申请日：2005-10-11

    Applicant: Mark A. Helm ,  Roger W. Lindsay

    Inventor： Mark A. Helm ,  Roger W. Lindsay

    IPC: H01L21/336

    CPC classification number: H01L27/11524 ,  G11C16/0483 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11521

    Abstract: A source line is formed by forming a source slot in a bulk insulation layer overlying a substrate to expose a portion of a substrate within the source slot, where the exposed portion of the substrate includes source regions of select gates associated with two or more columns of serially-connected floating-gate transistors formed on the substrate. A layer of epitaxial silicon is grown on the exposed portion so as to partially fill the source slot. A conductive layer is formed on the bulk insulation layer and on the layer of epitaxial silicon so as to substantially fill an unfilled portion of the source slot. The conductive layer is removed from a surface of the bulk insulation layer.

    Abstract translation: 源极线通过在覆盖衬底的体绝缘层中形成源极槽而形成，以暴露源极间隙内的衬底的一部分，其中衬底的暴露部分包括与两个或更多个列相关联的选择栅极的源极区域 形成在基板上的串联连接的浮栅晶体管。 在暴露部分上生长外延硅层，以便部分地填充源极槽。 导电层形成在体绝缘层和外延硅层上，以便基本上填充源槽的未填充部分。 从主体绝缘层的表面去除导电层。

    Methods of forming an array of flash field effect transistors and circuitry peripheral to such array
    3.
    发明授权
    Methods of forming an array of flash field effect transistors and circuitry peripheral to such array 有权
    形成闪存场效应晶体管阵列和这种阵列外围电路的方法

    公开(公告)号：US06759298B2

    公开(公告)日：2004-07-06

    申请号：US10179868

    申请日：2002-06-24

    Applicant: Roger W Lindsay ,  Mark A. Helm

    Inventor： Roger W Lindsay ,  Mark A. Helm

    IPC: H01L21336

    CPC classification number: H01L27/11526 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11536

    Abstract: A method of forming an array of FLASH field effect transistors and circuitry peripheral to such array includes forming a sacrificial oxide over an array area and a periphery area of a semiconductor substrate. After forming the sacrificial oxide, at least one conductivity modifying implant is conducted into semiconductive material of the substrate within the array without conducting the one conductivity modifying implant into semiconductive material of the substrate within the periphery. The sacrificial oxide is removed from the array while the sacrificial oxide is left over the periphery. After removing the sacrificial oxide from the array, at least some FLASH transistor gates are formed within the array and at least some non-FLASH transistor gates are formed within the periphery.

    Abstract translation: 形成FLASH场效应晶体管阵列和这种阵列外围的电路的方法包括在半导体衬底的阵列区域和外围区域上形成牺牲氧化物。 在形成牺牲氧化物之后，将至少一个电导率修饰注入物导入阵列内的衬底的半导体材料中，而不会将一个电导率修饰植入物导入周围的衬底半导体材料。 牺牲氧化物从阵列中除去，而牺牲氧化物留在周边。 在从阵列中除去牺牲氧化物之后，在阵列内形成至少一些闪存晶体管栅极，并在外围形成至少一些非闪存晶体管栅极。

    Methods of forming an array of FLASH field effect transistors and circuitry peripheral to the array
    4.
    发明授权
    Methods of forming an array of FLASH field effect transistors and circuitry peripheral to the array 有权
    形成阵列阵列的FLASH场效应晶体管和外围电路的方法

    公开(公告)号：US06579763B1

    公开(公告)日：2003-06-17

    申请号：US10179894

    申请日：2002-06-24

    Applicant: Roger W Lindsay

    Inventor： Roger W Lindsay

    IPC: H01L21336

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11536

    Abstract: A method of forming an array of FLASH field effect transistors and circuitry peripheral to the array includes etching periphery active area semiconductive material of a substrate substantially selectively relative to periphery field isolation while not etching array active area semiconductive material. After the periphery active area etching, at least some FLASH transistor control gate material is formed within the array and at least some non-FLASH transistor gate material is formed within the periphery. A method masking array active area semiconductive material while periphery active area semiconductive material is etched substantially selectively relative to the periphery field isolation. After the etching, the masking is removed. Thereafter, at least some FLASH transistor control gate material is formed within the array and at least some non-FLASH transistor gate material is formed within the periphery.

    Abstract translation: 形成FLASH场效应晶体管阵列和阵列外围的电路的方法包括基本上选择性地相对于外围场隔离蚀刻衬底的外围有源区半导体材料，而不蚀刻阵列有源区半导体材料。 在外围有源区域蚀刻之后，在阵列内形成至少一些FLASH晶体管控制栅极材料，并且在周边内形成至少一些非FLASH晶体管栅极材料。 一种掩模阵列有源区半导体材料的方法，而外围有源区半导体材料相对于外围场隔离被大大选择性地蚀刻。 蚀刻后，去除掩模。 此后，在阵列内形成至少一些闪存晶体管控制栅极材料，并且在周边内形成至少一些非闪存晶体管栅极材料。

    Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tier
    5.
    发明授权
    Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tier 有权
    包括半导体层残留硅化物的多层半导体装置

    公开(公告)号：US08872252B2

    公开(公告)日：2014-10-28

    申请号：US13197557

    申请日：2011-08-03

    Applicant: Anurag Jindal ,  Gowri Damarla ,  Roger W. Lindsay ,  Eric Blomiley

    Inventor： Anurag Jindal ,  Gowri Damarla ,  Roger W. Lindsay ,  Eric Blomiley

    IPC: H01L29/788 ,  H01L27/115 ,  H01L21/3213 ,  H01L21/02

    CPC classification number: H01L21/28273 ,  H01L21/02057 ,  H01L21/32134 ,  H01L27/11556

    Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

    Abstract translation: 描述形成多层半导体器件的方法以及包括它们的器件。 在一种这样的方法中，硅化物形成在硅层中，硅化物被去除，并且器件至少部分地形成在被硅化物占据的空隙中。 一种这样的设备包括一层硅，在介电材料层之间具有空隙。 残余硅化物位于硅层和/或介电材料层上，并且至少部分地在空隙中形成器件。 还描述了另外的实施例。

    Memory arrays with rows of memory cells coupled to opposite sides of a control gate
    6.
    发明授权
    Memory arrays with rows of memory cells coupled to opposite sides of a control gate 有权
    具有耦合到控制栅极的相对侧的存储器单元行的存储器阵列

    公开(公告)号：US08803228B2

    公开(公告)日：2014-08-12

    申请号：US13359947

    申请日：2012-01-27

    Applicant: Roger W. Lindsay ,  Lyle Jones

    Inventor： Roger W. Lindsay ,  Lyle Jones

    IPC: H01L29/66

    CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/7881

    Abstract: A memory array includes a control gate, where every memory cell coupled to a first side of the control gate is within a first row of memory cells and every memory cell coupled to a second side of the control gate is within a second row of memory cells, and where the first row of memory cells is successively adjacent to the second row of memory cells. The memory array also includes alternating first and second bit lines, where each of the memory cells of the first row of memory cells is coupled to a respective one of the first bit lines, where each of the memory cells of the second row of memory cells is coupled to a respective one of the second bit lines, and wherein the first bit lines are different from the second bit lines.

    Abstract translation: 存储器阵列包括控制栅极，其中耦合到控制栅极的第一侧的每个存储器单元位于第一行存储器单元内，并且耦合到控制栅极的第二侧的每个存储单元位于第二行存储器单元内 并且其中第一行存储器单元连续地邻近第二行存储器单元。 存储器阵列还包括交替的第一和第二位线，其中第一行存储器单元的每个存储器单元耦合到第一位线中的相应一个，其中第二行存储器单元的每个存储器单元 耦合到所述第二位线中的相应一个，并且其中所述第一位线与所述第二位线不同。

    APPARATUSES AND METHODS OF FORMING APPARATUSES USING A PARTIAL DECK-BY-DECK PROCESS FLOW
    8.
    发明申请
    APPARATUSES AND METHODS OF FORMING APPARATUSES USING A PARTIAL DECK-BY-DECK PROCESS FLOW 审中-公开
    使用部分DECK-BY-DECK工艺流程形成装置的装置和方法

    公开(公告)号：US20130277731A1

    公开(公告)日：2013-10-24

    申请号：US13450299

    申请日：2012-04-18

    Applicant: Akira Goda ,  Roger W. Lindsay

    Inventor： Akira Goda ,  Roger W. Lindsay

    IPC: H01L27/088 ,  H01L21/8239 ,  H01L27/08 ,  H01L21/822

    CPC classification number: G11C16/0408 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Various embodiments include methods and apparatuses, such as memory cells formed on two or more stacked decks. A method includes forming a first deck with first levels of conductor material and first levels of dielectric material over a substrate. Each level of the conductor material is separated from an adjacent level of conductor material by at least one of the first levels of dielectric material. A first opening is formed through the first levels of conductor material and dielectric material. A sacrificial material is formed at least partially filling the first opening. A second deck is formed over the first deck. The second deck has second levels of conductor material and second levels of dielectric material with each level of the conductor material being separated from an adjacent level of conductor material by at least one of the second levels of dielectric material. Additional apparatuses and methods are disclosed.

    Abstract translation: 各种实施例包括诸如形成在两个或更多个堆叠甲板上的存储单元的方法和装置。 一种方法包括在衬底上形成具有第一级导体材料和第一级电介质材料的第一层板。 导体材料的每个级别通过第一级介电材料中的至少一个与相邻级别的导体材料分开。 通过导体材料和电介质材料的第一层形成第一开口。 形成至少部分地填充第一开口的牺牲材料。 在第一层甲板上形成第二层甲板。 第二层具有第二层导体材料和第二层介质材料，其中导电材料的每一层通过至少一个第二层介质材料与相邻层的导体材料分开。 公开了附加的装置和方法。

    METHODS OF FORMING A MULTI-TIERED SEMICONDUCTOR DEVICE AND APPARATUSES INCLUDING THE SAME
    9.
    发明申请
    METHODS OF FORMING A MULTI-TIERED SEMICONDUCTOR DEVICE AND APPARATUSES INCLUDING THE SAME 有权
    形成多层半导体器件的方法和包括其的装置

    公开(公告)号：US20130032870A1

    公开(公告)日：2013-02-07

    申请号：US13197557

    申请日：2011-08-03

    Applicant: Anurag Jindal ,  Gowri Damarla ,  Roger W. Lindsay ,  Eric Blomiley

    Inventor： Anurag Jindal ,  Gowri Damarla ,  Roger W. Lindsay ,  Eric Blomiley

    IPC: H01L29/788 ,  H01L29/792 ,  H01L21/30 ,  H01L21/28 ,  H01L21/306

    CPC classification number: H01L21/28273 ,  H01L21/02057 ,  H01L21/32134 ,  H01L27/11556

    Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

    Abstract translation: 描述形成多层半导体器件的方法以及包括它们的器件。 在一种这样的方法中，硅化物形成在硅层中，硅化物被去除，并且器件至少部分地形成在被硅化物占据的空隙中。 一种这样的设备包括一层硅，在介电材料层之间具有空隙。 残余硅化物位于硅层和/或介电材料层上，并且至少部分地在空隙中形成器件。 还描述了另外的实施例。

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