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    Memory arrays and methods of fabricating memory arrays
    1.
    发明授权
    Memory arrays and methods of fabricating memory arrays 有权
    存储器阵列和制造存储器阵列的方法

    公开(公告)号：US08394699B2

    公开(公告)日：2013-03-12

    申请号：US12828915

    申请日：2010-07-01

    申请人： Gordon A. Haller ,  Sanh D. Tang

    发明人： Gordon A. Haller ,  Sanh D. Tang

    IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/66621 ,  G11C11/405 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/10891

    摘要： A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.

    摘要翻译： 存储器阵列包括形成在半导体衬底上的多个存储单元。 存储单元的个体包括分别包括栅极，沟道区和一对源极/漏极区的第一和第二场效应晶体管。 第一和第二场效应晶体管的栅极被硬连线在一起。 导电数据线硬连接到两个源极/漏极区域。 电荷存储装置硬连接到除二者之外的源极/漏极区域中的至少一个。 考虑了其他方面和实现方式，包括制造存储器阵列的方法。

    Semiconductor Processing Methods, And Methods Of Forming Isolation Structures
    2.
    发明申请
    Semiconductor Processing Methods, And Methods Of Forming Isolation Structures 有权
    半导体加工方法和形成隔离结构的方法

    公开(公告)号：US20120329231A1

    公开(公告)日：2012-12-27

    申请号：US13603100

    申请日：2012-09-04

    申请人： Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    发明人： Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    IPC分类号： H01L21/762 ,  H01L21/336

    CPC分类号： H01L21/823462 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823481 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7846

    摘要： Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

    摘要翻译： 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料（例如，聚硅氮烷）可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后，可以将一种或多种掺杂剂物质注入到投影中，使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构，其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域，其中上部区域为至少75％的无定形，并且下部区域是完全结晶的。

    Transistor Gate Forming Methods and Transistor Structures
    3.
    发明申请
    Transistor Gate Forming Methods and Transistor Structures 有权
    晶体管栅极形成方法和晶体管结构

    公开(公告)号：US20110092062A1

    公开(公告)日：2011-04-21

    申请号：US12977969

    申请日：2010-12-23

    申请人： Sanh D. Tang ,  Gordon A. Haller ,  Prashant Raghu ,  Ravi Iyer

    发明人： Sanh D. Tang ,  Gordon A. Haller ,  Prashant Raghu ,  Ravi Iyer

    IPC分类号： H01L21/28

    CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66787

    摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

    摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。

    Peripheral gate stacks and recessed array gates
    5.
    发明授权
    Peripheral gate stacks and recessed array gates 有权
    外围栅极堆叠和凹陷阵列栅极

    公开(公告)号：US07416943B2

    公开(公告)日：2008-08-26

    申请号：US11219304

    申请日：2005-09-01

    申请人： Thomas A. Figura ,  Gordon A. Haller

    发明人： Thomas A. Figura ,  Gordon A. Haller

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823456 ,  H01L21/82345 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897

    摘要： Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.

    摘要翻译： 提供了用于在集成电路的两个不同区域中同时处理晶体管的方法。 在逻辑区域中提供平面晶体管，而在用于存储器件的阵列区域中提供凹入式存取设备（RAD）。 在周边的栅堆栈图案化期间，字线凹入用于阵列RAD的沟槽内。 在外围的侧壁间隔物形成同时提供了一个绝缘盖层，掩埋了阵列的沟槽内的字线。

    Vertical transistors
    6.
    发明授权
    Vertical transistors 有权
    垂直晶体管

    公开(公告)号：US07285812B2

    公开(公告)日：2007-10-23

    申请号：US10934621

    申请日：2004-09-02

    申请人： Sanh Dang Tang ,  Gordon A. Haller

    发明人： Sanh Dang Tang ,  Gordon A. Haller

    IPC分类号： H01L29/76

    CPC分类号： H01L27/10885 ,  H01L21/28132 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66666

    摘要： Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the lower active area. Vertical transistor pillars can be formed from epitaxial silicon or etched from bulk silicon. Memory cells can be formed by creating a cell capacitor electrically connected to each transistor pillar.

    摘要翻译： 公开了用于存储器单元的垂直晶体管，例如4F2存储器单元。 存储单元使用形成在隔离沟槽内的数字线连接来将数字线连接到较低有效区域。 垂直晶体管柱可以由外延硅形成，也可以从体硅中蚀刻。 可以通过产生电连接到每个晶体管柱的单元电容器来形成存储单元。

    Memory structure for reduced floating body effect
    8.
    发明授权
    Memory structure for reduced floating body effect 有权
    用于减少浮体效应的记忆结构

    公开(公告)号：US07199419B2

    公开(公告)日：2007-04-03

    申请号：US11010752

    申请日：2004-12-13

    申请人： Gordon A. Haller

    发明人： Gordon A. Haller

    IPC分类号： H01L27/108

    CPC分类号： H01L27/0218 ,  H01L27/10823 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10891

    摘要： Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a word line is recessed into the substrate to tie the upper active region to the substrate. The resulting memory cells are preferably used in dynamic random access memory (DRAM) devices.

    摘要翻译： 公开了降低垂直晶体管中的浮体效应的方法。 当通过耗尽区从衬底切断柱中的有源区域并产生伴随的静电势时，发生浮体效应。 在一个优选实施例中，字线凹陷到衬底中以将上部有源区域连接到衬底。 所得到的存储单元优选地用于动态随机存取存储器（DRAM）装置。

    ALUMINUM OXIDE LANDING LAYER FOR CONDUCTIVE CHANNELS FOR A THREE DIMENSIONAL CIRCUIT DEVICE
    10.
    发明申请
    ALUMINUM OXIDE LANDING LAYER FOR CONDUCTIVE CHANNELS FOR A THREE DIMENSIONAL CIRCUIT DEVICE 有权
    用于三维电路设备的导电通道的氧化铝接地层

    公开(公告)号：US20160133640A1

    公开(公告)日：2016-05-12

    申请号：US14329644

    申请日：2014-07-11

    申请人： HONGBIN ZHU ,  GORDON A. HALLER ,  FATMA A. SIMSEK-EGE

    发明人： HONGBIN ZHU ,  GORDON A. HALLER ,  FATMA A. SIMSEK-EGE

    IPC分类号： H01L27/115

    CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11558

    摘要： A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.

    摘要翻译： 具有氧化铝（AlOx）层作为贵金属HiK层的多层堆叠的存储单元以提供蚀刻停止选择性。 堆叠的每层包括存储单元设备。 该电路包括与存储器单元的多层堆叠相邻的源极选择多晶（SGS多晶）层，其中SGS多晶硅层为多层堆叠的存储单元提供栅极选择信号。 该电路还包括导电源层，以为层叠层的通道提供源极导体。 AlOx层设置在源层和SGS多晶硅层之间，并提供干蚀刻选择性和湿蚀刻选择性，以创建用于将存储单元电耦合到源层的通道。