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    Peripheral Gate Stacks and Recessed Array Gates
    3.
    发明申请
    Peripheral Gate Stacks and Recessed Array Gates 有权
    外围门堆叠和嵌入式阵列门

    公开(公告)号：US20080299753A1

    公开(公告)日：2008-12-04

    申请号：US12177296

    申请日：2008-07-22

    申请人： Thomas A. Figura ,  Gordon A. Haller

    发明人： Thomas A. Figura ,  Gordon A. Haller

    IPC分类号： H01L21/28

    CPC分类号： H01L21/823456 ,  H01L21/82345 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897

    摘要： Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.

    摘要翻译： 提供了用于在集成电路的两个不同区域中同时处理晶体管的方法。 在逻辑区域中提供平面晶体管，而在用于存储器件的阵列区域中提供凹入式存取设备（RAD）。 在周边的栅堆栈图案化期间，字线凹入用于阵列RAD的沟槽内。 在外围的侧壁间隔物形成同时提供了一个绝缘盖层，掩埋了阵列的沟槽内的字线。

    Peripheral gate stacks and recessed array gates
    5.
    发明授权
    Peripheral gate stacks and recessed array gates 有权
    外围栅极堆叠和凹陷阵列栅极

    公开(公告)号：US07416943B2

    公开(公告)日：2008-08-26

    申请号：US11219304

    申请日：2005-09-01

    申请人： Thomas A. Figura ,  Gordon A. Haller

    发明人： Thomas A. Figura ,  Gordon A. Haller

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823456 ,  H01L21/82345 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897

    摘要： Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.

    摘要翻译： 提供了用于在集成电路的两个不同区域中同时处理晶体管的方法。 在逻辑区域中提供平面晶体管，而在用于存储器件的阵列区域中提供凹入式存取设备（RAD）。 在周边的栅堆栈图案化期间，字线凹入用于阵列RAD的沟槽内。 在外围的侧壁间隔物形成同时提供了一个绝缘盖层，掩埋了阵列的沟槽内的字线。

    Peripheral Gate Stacks and Recessed Array Gates
    6.
    发明申请
    Peripheral Gate Stacks and Recessed Array Gates 有权
    外围门堆叠和嵌入式阵列门

    公开(公告)号：US20110183507A1

    公开(公告)日：2011-07-28

    申请号：US13083782

    申请日：2011-04-11

    申请人： Thomas A. Figura ,  Gordon A. Haller

    发明人： Thomas A. Figura ,  Gordon A. Haller

    IPC分类号： H01L21/28

    CPC分类号： H01L21/823456 ,  H01L21/82345 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897

    摘要： Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.

    摘要翻译： 提供了用于在集成电路的两个不同区域中同时处理晶体管的方法。 在逻辑区域中提供平面晶体管，而在用于存储器件的阵列区域中提供凹入式存取设备（RAD）。 在周边的栅堆栈图案化期间，字线凹入用于阵列RAD的沟槽内。 在外围的侧壁间隔物形成同时提供了一个绝缘盖层，掩埋了阵列的沟槽内的字线。

    Peripheral gate stacks and recessed array gates
    8.
    发明授权
    Peripheral gate stacks and recessed array gates 有权
    外围栅极堆叠和凹陷阵列栅极

    公开(公告)号：US07939409B2

    公开(公告)日：2011-05-10

    申请号：US12177296

    申请日：2008-07-22

    申请人： Thomas A. Figura ,  Gordon A. Haller

    发明人： Thomas A. Figura ,  Gordon A. Haller

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823456 ,  H01L21/82345 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897

    摘要： Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.

    摘要翻译： 提供了用于在集成电路的两个不同区域中同时处理晶体管的方法。 在逻辑区域中提供平面晶体管，而在用于存储器件的阵列区域中提供凹入式存取设备（RAD）。 在周边的栅堆栈图案化期间，字线凹入用于阵列RAD的沟槽内。 在外围的侧壁间隔物形成同时提供了一个绝缘盖层，掩埋了阵列的沟槽内的字线。

    Semiconductor processing methods, and methods of forming isolation structures
    9.
    发明授权
    Semiconductor processing methods, and methods of forming isolation structures 有权
    半导体加工方法和形成隔离结构的方法

    公开(公告)号：US08906771B2

    公开(公告)日：2014-12-09

    申请号：US13603100

    申请日：2012-09-04

    申请人： Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    发明人： Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L21/823462 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823481 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7846

    摘要： Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

    摘要翻译： 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料（例如，聚硅氮烷）可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后，可以将一种或多种掺杂剂物质注入到投影中，使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构，其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域，其中上部区域为至少75％的无定形，并且下部区域是完全结晶的。

    Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells
    10.
    发明授权
    Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells 有权
    形成场效应晶体管，多个场效应晶体管和包括多个单独存储单元的DRAM电路的方法

    公开(公告)号：US08409946B2

    公开(公告)日：2013-04-02

    申请号：US13528028

    申请日：2012-06-20

    申请人： Paul Grisham ,  Gordon A. Haller ,  Sahn D. Tang

    发明人： Paul Grisham ,  Gordon A. Haller ,  Sahn D. Tang

    IPC分类号： H01L21/8236

    CPC分类号： H01L29/7851 ,  H01L21/76232 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66818 ,  H01L29/7854

    摘要： A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed.

    摘要翻译： 形成场效应晶体管的方法包括在半导体衬底内形成沟槽隔离材料，并在沟道区的长度上在半导体材料沟道区的相对侧上形成沟道隔离材料。 沟槽隔离材料形成为包括沿着沟道长度部分地在沟道区域下方朝向彼此延伸的相对的绝缘突起，并且半导体材料被接收在突起上。 蚀刻沟槽隔离材料以沿着沟道长度露出半导体材料的相对侧。 半导体材料的暴露的相对侧沿通道长度被蚀刻以形成相对于突出部向上突出的通道翅片。 栅极沿着沟道长度形成在鳍的顶部和相对侧上。 公开了其它方法和结构。