公开(公告)号：US06834008B2

公开(公告)日：2004-12-21

申请号：US10330153

申请日：2002-12-26

Applicant: Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

IPC: G11C1100

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  G11C2213/77

Abstract: Cross point memory array using multiple modes of operation. The invention is a cross point memory array that uses a read mode to determine the resistive state of a memory plug, a first write mode to cause the memory plug to change from a first resistive state to a second resistive state, and a second write mode to cause the memory plug to change from the second resistive state back to the first resistive state.

Abstract translation: 交叉点存储器阵列使用多种操作模式。 本发明是一种交叉点存储器阵列，其使用读取模式来确定存储器插头的电阻状态，使得存储器插头从第一电阻状态改变到第二电阻状态的第一写入模式和第二写入模式 以使存储器插头从第二电阻状态转变回第一电阻状态。

公开(公告)号：US06831854B2

公开(公告)日：2004-12-14

申请号：US10330964

申请日：2002-12-26

Applicant: Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

IPC: G11C1102

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/77

Abstract: Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines uniquely defining a single memory plug. The magnitude of the select voltages depends upon whether a read operation or a write operation is occurring. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage is approximately equal to the average of the first select voltage and the second select voltage.

Abstract translation: 交叉点存储器阵列使用不同的电压。 本发明是一种交叉点存储器阵列，其在一个导电阵列线上施加第一选择电压，在第二导电阵列线上施加第二选择电压，所述两个导电阵列线唯一地限定单个存储器插头。 选择电压的大小取决于是否发生读取操作或写入操作。 此外，未选择的电压被施加到未选择的导电阵列线。 可以在选择过程之前，之后或期间施加取消选择电压。 取消选择电压近似等于第一选择电压和第二选择电压的平均值。

公开(公告)号：US06798685B2

公开(公告)日：2004-09-28

申请号：US10330150

申请日：2002-12-26

Applicant: Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia

IPC: G11C1100

CPC classification number: G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

Abstract: Providing a multi-output multiplexor. The invention is multi-output multiplexor that, depending on the control signals, allows various modulating circuits to pass no voltage, pass some voltage or pass all the voltage on one of the multiplexor's ports. A modulating circuit can be fully turned on, partially turned on, or fully turned off. In a preferred embodiment, a gate circuit is in electrical contact with ground such that when the gate circuit is turned on and its associated modulating curcuit is not passing voltage, the multiplexor output associated with the modulating curcuit goes to ground.

Abstract translation: 提供多输出多路复用器。 本发明是多输出多路复用器，其根据控制信号允许各种调制电路不传递电压，传递一些电压或传递多路复用器端口之一上的所有电压。 调制电路可以完全打开，部分打开或完全关闭。 在优选实施例中，门电路与接地电接触，使得当门电路接通并且其相关联的调制电路不通过电压时，与调制电路相关联的多路复用器输出接地。

公开(公告)号：US08395928B2

公开(公告)日：2013-03-12

申请号：US13206460

申请日：2011-08-09

Applicant: Julie Casperson Brewer ,  Christophe Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Darrell Rinerson ,  Lawrence Schloss

Inventor： Julie Casperson Brewer ,  Christophe Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Darrell Rinerson ,  Lawrence Schloss

IPC: G11C11/36

CPC classification number: G11C7/02 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147

Abstract: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

公开(公告)号：US08314024B2

公开(公告)日：2012-11-20

申请号：US12454322

申请日：2009-05-15

Applicant: Darrell Rinerson ,  Robin Cheung

Inventor： Darrell Rinerson ,  Robin Cheung

IPC: H01L21/768

CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

公开(公告)号：US20120075914A1

公开(公告)日：2012-03-29

申请号：US13252934

申请日：2011-10-04

Applicant: BRUCE BATEMAN ,  DARRELL RINERSON ,  CHRISTOPHE CHEVALLIER ,  CHANG HUA SIAU

Inventor： BRUCE BATEMAN ,  DARRELL RINERSON ,  CHRISTOPHE CHEVALLIER ,  CHANG HUA SIAU

IPC: G11C11/00

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/77

Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

Abstract translation: 用于存储器的低读取当前体系结构。 允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。

公开(公告)号：US07897951B2

公开(公告)日：2011-03-01

申请号：US11881496

申请日：2007-07-26

Applicant: Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

Inventor： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

IPC: H01L29/02 ,  H01L29/06

CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

公开(公告)号：US07884349B2

公开(公告)日：2011-02-08

申请号：US12283339

申请日：2008-09-11

Applicant: Darrell Rinerson ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe J. Chevallier

Inventor： Darrell Rinerson ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe J. Chevallier

IPC: H01L29/06

CPC classification number: H01L27/101 ,  G11C11/00 ,  G11C11/56 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/00 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/147

Abstract: A memory cell including a memory element and a non-ohmic device (NOD) that are electrically in series with each other is disclosed. The NOD comprises a semiconductor based selection device operative to electrically isolate the memory element from a range of voltages applied across the memory cell that are not read voltages operative read stored data from the memory element or write voltages operative to write data to the memory element. The selection device may comprise a pair of diodes that are electrically in series with each other and disposed in a back-to-back configuration. The memory cell may be fabricated over a substrate (e.g., a silicon wafer) that includes active circuitry. The selection device and the semiconductor materials (e.g., poly-silicon) that form the selection device are fabricated above the substrate and are integrated with other thin film layers of material that form the memory cell.

Abstract translation: 公开了一种包括彼此电串联的存储元件和非欧姆器件（NOD）的存储单元。 NOD包括基于半导体的选择装置，其操作以将存储器元件与施加在存储器单元上的电压范围电隔离，所述电压范围不是读取电压，从存储元件读取存储的数据，或者写入电压可操作以将数据写入存储器元件。 选择装置可以包括彼此电连接并以背对背配置设置的一对二极管。 可以在包括有源电路的衬底（例如，硅晶片）上制造存储器单元。 形成选择装置的选择装置和半导体材料（例如，多晶硅）制造在衬底之上，并与形成存储单元的材料的其它薄膜层集成。

公开(公告)号：US20100265762A1

公开(公告)日：2010-10-21

申请号：US12803214

申请日：2010-06-21

Applicant: Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hasen

Inventor： Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hasen

IPC: G11C11/00 ,  H01L45/00

CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165 ,  Y10S257/903

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include anon-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract translation: 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电连接的欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。

公开(公告)号：US20100159641A1

公开(公告)日：2010-06-24

申请号：US12653851

申请日：2009-12-18

Applicant: Darrell Rinerson ,  Jonathan Bornstein ,  David Hansen ,  Robin Cheung ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

Inventor： Darrell Rinerson ,  Jonathan Bornstein ,  David Hansen ,  Robin Cheung ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

IPC: H01L21/34

CPC classification number: F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Abstract translation: 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。