公开(公告)号：US10553713B2

公开(公告)日：2020-02-04

申请号：US15286055

申请日：2016-10-05

Applicant: ROHM CO., LTD.

Inventor： Yuki Nakano

IPC: H01L29/772 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08 ,  H01L29/04

Abstract: The present invention provides a semiconductor device that can achieve both low on-resistance and high withstand voltage, while reducing the device size, improving the manufacturing yield, and reducing the cost. The semiconductor device 1 includes a substrate 5, an epitaxial layer 6 formed on the substrate 5 and formed with a gate trench 11, a gate insulating film 17 formed on the side surface 14 and the bottom surface 15 of the gate trench 11, a gate electrode 20 embedded in the gate trench 11 and opposed to the epitaxial layer 6 with the gate insulating film 17 therebetween, and a source layer 25, a channel layer 26, and a drift layer 27 formed in this order from a first surface to a second surface of the epitaxial layer 6, in which the on-resistance Ron represented by a variable “y” and the withstand voltage Vb represented by a variable “x” functionally satisfy the following relational expression (1): y≤9×10−7x2−0.0004x+0.7001  (1).

公开(公告)号：US10449573B2

公开(公告)日：2019-10-22

申请号：US15634137

申请日：2017-06-27

Applicant: Johan Calcoen ,  Peter Stulens

Inventor： Johan Calcoen ,  Peter Stulens

IPC: B07C5/36 ,  H01L31/024 ,  B07C5/34 ,  G01J1/42 ,  G01J1/44 ,  H01L25/16 ,  H01L31/107 ,  B07C5/342 ,  G01J1/02 ,  H01L29/772

Abstract: A sorting apparatus is described and which includes a selectively heated avalanche photodiode (APD) which is maintained at a predetermined temperature and which further demonstrates a higher gain and signal-to-noise ratio with greater stability at a predetermined temperature for enhancing sorting efficiency.

公开(公告)号：US10276703B2

公开(公告)日：2019-04-30

申请号：US15619679

申请日：2017-06-12

Applicant: FUJITSU LIMITED

Inventor： Youichi Kamada ,  Shirou Ozaki

IPC: H01L29/772 ,  H01L29/778 ,  H01L29/66 ,  H01L23/29 ,  H01L23/31 ,  H01L29/423 ,  H01L29/20

Abstract: A compound semiconductor device includes: a carrier transit layer; a carrier supply layer over the carrier transit layer; a source electrode and a drain electrode above the carrier supply layer; a gate electrode above the carrier supply layer between the source electrode and the drain electrode; and a first insulating film and a second insulating film above the carrier supply layer between the gate electrode and the drain electrode. The gate electrode includes a portion above the second insulating film, the second insulating film covers a side surface of the first insulating film from the drain electrode side, and a second concentration of electron traps in the second insulating film is higher than a first concentration of electron traps in the first insulating film.

公开(公告)号：US10269802B2

公开(公告)日：2019-04-23

申请号：US14714231

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Han Lin

IPC: H01L29/772 ,  H01L27/092 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/3213

Abstract: A semiconductor device includes first and second Fin FETs and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending in a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending in the second direction. When viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate electrode abutting the separation plug has a convex curved shape.

公开(公告)号：US10224321B2

公开(公告)日：2019-03-05

申请号：US15242684

申请日：2016-08-22

Applicant: MagnaChip Semiconductor, Ltd.

Inventor： Francois Hebert

IPC: H01L27/06 ,  H01L27/07 ,  H01L29/772 ,  H01L29/872 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49

Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.

公开(公告)号：US10147895B2

公开(公告)日：2018-12-04

申请号：US15209710

申请日：2016-07-13

Applicant: Flexterra, Inc.

Inventor： Shaofeng Lu ,  Antonio Facchetti ,  Xiang Yu ,  Darwin Scott Bull ,  Karen K. Chan

IPC: C08G65/02 ,  C08G65/06 ,  H01L51/10 ,  H01L51/05 ,  C08G61/12 ,  H01L51/00 ,  C08G61/08 ,  H01L29/47 ,  H01L29/786 ,  H01L29/772

Abstract: The present teachings relate to curable linear polymers that can be used as active and/or passive organic materials in various electronic, optical, and optoelectronic devices. In some embodiments, the device can include an organic semiconductor layer and a dielectric layer prepared from such curable linear polymers. In some embodiments, the device can include a passivation layer prepared from the linear polymers described herein. The present linear polymers can be solution-processed, then cured thermally (particularly, at relatively low temperatures) and/or photochemically into various thin film materials with desirable properties.

公开(公告)号：US10141412B2

公开(公告)日：2018-11-27

申请号：US15333442

申请日：2016-10-25

Applicant: National Taiwan University ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yuh-Renn Wu ,  Chi-Wen Liu ,  Shou-Fang Chen

IPC: H01L29/06 ,  H01L29/772 ,  H01L29/24 ,  H01L29/04 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A field effect transistor (FET) includes a gate dielectric layer, a two-dimensional (2D) channel layer formed on the gate dielectric layer and a gate electrode. The 2D channel layer includes a body region having a first side and a second side opposite to the first side, the body region being a channel of the FET. The 2D channel layer further includes first finger regions each protruding from the first side of the body region and second finger regions each protruding from the second side of the body region. A source electrode covers the first finger regions, and a drain electrode covers the second finger regions.

公开(公告)号：US10128231B2

公开(公告)日：2018-11-13

申请号：US15794876

申请日：2017-10-26

Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

Inventor： Zhongshan Hong

IPC: H01L21/02 ,  H01L21/461 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02 ,  H01L29/66 ,  H01L29/772

Abstract: An integrated device includes a field effect transistor formed within and upon an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. The resistor includes a resistor body being an enclosure portion of the first conductive layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body. A method for manufacturing a semiconductor device includes forming a gate stacked structure and a resistor stacked structure at the same time by patterning a dielectric layer, a first conductive layer and a second conductive layer. The method also includes forming a resistor having a resistor body by patterning the resistor stacked structure.

公开(公告)号：US09972493B2

公开(公告)日：2018-05-15

申请号：US15594883

申请日：2017-05-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/306 ,  G11C16/04 ,  H01L29/772 ,  H01L29/423

CPC classification number: H01L21/28 ,  G11C16/0425 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/772

Abstract: A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

公开(公告)号：US20180053828A1

公开(公告)日：2018-02-22

申请号：US15794526

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mohit BAJAJ ,  Suresh GUNDAPANENI ,  Aniruddha KONAR ,  Narasimha R. Mavilla ,  Kota V.R.M. MURALI ,  Edward J. NOWAK

IPC: H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/78 ,  H01L29/772 ,  H01L29/739 ,  H01L29/66 ,  H01L29/267 ,  H01L29/24 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8232 ,  H01L21/3115

CPC classification number: H01L29/41725 ,  H01L21/02414 ,  H01L21/02483 ,  H01L21/02565 ,  H01L21/02581 ,  H01L21/3115 ,  H01L21/8232 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/205 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/772 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78693

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.