公开(公告)号：US20240387397A1

公开(公告)日：2024-11-21

申请号：US18786474

申请日：2024-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

IPC: H01L23/544 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.

公开(公告)号：US20240379821A1

公开(公告)日：2024-11-14

申请号：US18783512

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L21/027 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

公开(公告)号：US20240379818A1

公开(公告)日：2024-11-14

申请号：US18779849

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

Abstract: A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

公开(公告)号：US12142609B2

公开(公告)日：2024-11-12

申请号：US18354844

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Yun-Ting Chou ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L27/092 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

公开(公告)号：US20240371644A1

公开(公告)日：2024-11-07

申请号：US18778304

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.

公开(公告)号：US11948835B2

公开(公告)日：2024-04-02

申请号：US17230701

申请日：2021-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/528

CPC classification number: H01L21/76831 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L23/528 ,  H01L21/76804 ,  H01L23/485

Abstract: A device comprises a first metal structure, a dielectric structure, a dielectric residue, and a second metal structure. The dielectric structure is over the first metal structure. The dielectric structure has a stepped sidewall structure. The stepped sidewall structure comprises a lower sidewall and an upper sidewall laterally set back from the lower sidewall. The dielectric residue is embedded in a recessed region in the lower sidewall of the stepped sidewall structure of the dielectric structure. The second metal structure extends through the dielectric structure to the first metal structure.

公开(公告)号：US11894277B2

公开(公告)日：2024-02-06

申请号：US17869590

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/823864 ,  H01L21/28123 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545

Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

公开(公告)号：US11854962B2

公开(公告)日：2023-12-26

申请号：US17106766

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/288 ,  H01L23/532 ,  H01L21/027 ,  H01L21/321 ,  H01L29/06

CPC classification number: H01L23/5226 ,  H01L21/0276 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/088 ,  H01L21/3212 ,  H01L21/7684 ,  H01L29/0649

Abstract: A semiconductor device includes a substrate, a bottom etch stop layer over the substrate, a middle etch stop layer over the bottom etch stop layer, and a top etch stop layer over the middle etch stop layer. The top, middle, and bottom etch stop layers include different material compositions from each other. The semiconductor device further includes a dielectric layer over the top etch stop layer and a via extending through the dielectric layer and the top, middle, and bottom etch stop layers. The via has a first sidewall in contact with the dielectric layer and slanted inwardly from top to bottom towards a center of the via and a second sidewall in contact with the bottom etch stop layer and slanted outwardly from top to bottom away from the center of the via.

公开(公告)号：US11837649B2

公开(公告)日：2023-12-05

申请号：US16939943

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785

Abstract: A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

公开(公告)号：US11784055B2

公开(公告)日：2023-10-10

申请号：US17692824

申请日：2022-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/31 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785 ,  H01L23/3157

Abstract: A method includes following steps. A substrate is etched using a hard mask as an etch mask to form a fin. A bottom anti-reflective coating (BARC) layer is over the fin. A recess is formed in the BARC layer to expose a first portion of the hard mask. A protective coating layer is formed at least on a sidewall of the recess in the BARC layer. A first etching step is performed to remove the first portion of the hard mask to expose a first portion of the fin, while leaving a second portion of the fin covered under the protective coating layer and the BARC layer. A second etching step is performed to lower a top surface of the first portion of the fin to below a top surface of the second portion of the fin.