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公开(公告)号：US20180337243A1
公开(公告)日：2018-11-22
申请号：US15973711
申请日：2018-05-08
Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
Inventor： Yong Li , Zhongshan Hong
IPC: H01L29/423 , H01L27/088 , H01L29/08 , H01L21/8234 , H01L21/28
CPC classification number: H01L29/42368 , H01L21/28211 , H01L21/823418 , H01L21/823431 , H01L21/823462 , H01L27/0886 , H01L29/0847
Abstract: This disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device may include a substrate; a first fin on the substrate for forming a first electronic component; a first gate structure on a portion of the first fin including a first gate dielectric layer on a portion of the first fin and a first gate on the first gate dielectric layer; and a first source region and a first drain region that each at one of two sides of the first gate structure and at least partially located in the first fin, where the first gate dielectric layer comprises a first region abutting against the first drain region, a second region abutting against the first source region, and a third region between the first region and the second region, and wherein thickness of the first region is greater than that of the third region.
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公开(公告)号：US09472422B2
公开(公告)日：2016-10-18
申请号：US14856545
申请日：2015-09-16
Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Inventor： Zhongshan Hong
IPC: H01L21/3213 , H01L21/768 , H01L27/115 , H01L23/522 , H01L23/528
CPC classification number: H01L21/32139 , H01L21/31144 , H01L21/76802 , H01L21/76838 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
Abstract: A method for forming a semiconductor device includes providing a semiconductor structure which has a substrate and N sub-stack structures numbered from 1 to N, where N is an integer. Each sub-stack structure includes two sub-stacks, and a mask layer overlying the N sub-stack structures. The method also includes repeatedly removing a portion of the mask layer and removing exposed portions of the sub-stack structures to form a first stepped structure, and forming first spacers on sidewalls of the mask layer and the sub-stack structures in the stepped structure, each spacer covering a portion of the exposure portions of the sub-stack structures. The method further includes using the mask layer and the first spacers as masks to remove exposed portions of an upper sub-stack in the first stepped structure, and removing the mask layer and the spacers to form a second stepped structure.
Abstract translation: 一种形成半导体器件的方法包括提供一种半导体结构，其具有衬底和编号为1至N的N个子堆叠结构，其中N为整数。 每个子堆栈结构包括两个子堆栈和覆盖N个子栈结构的掩码层。 该方法还包括重复地去除掩模层的一部分并去除子堆叠结构的暴露部分以形成第一阶梯结构，以及在阶梯状结构中在掩模层和子堆叠结构的侧壁上形成第一间隔物， 每个间隔物覆盖子堆叠结构的曝光部分的一部分。 该方法还包括使用掩模层和第一间隔物作为掩模以去除第一阶梯结构中的上部子堆叠的暴露部分，以及去除掩模层和间隔物以形成第二阶梯结构。
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公开(公告)号：US09548359B2
公开(公告)日：2017-01-17
申请号：US14863400
申请日：2015-09-23
Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Inventor： Zhongshan Hong
IPC: H01L21/76 , H01L29/06 , H01L21/3065 , H01L21/308 , H01L21/306
CPC classification number: H01L29/0676 , B82Y30/00 , H01L21/30625 , H01L21/3065 , H01L21/3081 , H01L21/3083 , H01L21/3086
Abstract: A method for forming a semiconductor device includes providing a semiconductor structure, which includes a semiconductor substrate and a first mask layer on the substrate. The first mask layer is used to form a plurality of first trenches that extends into the substrate and extends laterally in a first direction and do not intersect each other. The first trenches are then filled with a fill material. Next, a second mask layer is formed on the semiconductor structure filled with the fill material. The second mask layer is then used to form a second plurality of trenches in the semiconductor substrate that extend laterally in a second direction and do not intersect each other. Each of the second trenches intersects at least one of the first plurality of trenches. Next, the fill material is removed to form a plurality of vertical pillars defined by intersecting first trenches and second trenches.
Abstract translation: 一种形成半导体器件的方法包括提供半导体结构，该半导体结构在衬底上包括半导体衬底和第一掩模层。 第一掩模层用于形成多个第一沟槽，其延伸到衬底中并沿第一方向横向延伸并且不相交。 第一个沟槽然后填充填充材料。 接下来，在填充有填充材料的半导体结构上形成第二掩模层。 然后使用第二掩模层在半导体衬底中形成在第二方向上横向延伸并且不相交的第二多个沟槽。 每个第二沟槽与第一多个沟槽中的至少一个相交。 接下来，去除填充材料以形成由相交的第一沟槽和第二沟槽限定的多个垂直柱。
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公开(公告)号：US09984882B2
公开(公告)日：2018-05-29
申请号：US15275111
申请日：2016-09-23
Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
Inventor： Yong Li , Zhongshan Hong
CPC classification number: H01L21/28158 , H01L21/0214 , H01L21/02148 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02194 , H01L21/02247 , H01L21/02255 , H01L21/02332 , H01L21/02359 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66795
Abstract: A method for fabricating a semiconductor structure includes providing a substrate, forming an interface layer on the substrate, and then performing a first annealing process on the interface layer under a nitrogen-containing environment to form a nitrogen-containing layer from a top portion of the interface layer. The first annealing process also deactivates non-bonded silicon ions and oxygen ions in the interface layer. The method further includes forming a high-k dielectric layer on the nitrogen-containing layer, and performing a second annealing process on the high-k dielectric layer to allow nitrogen ions in the nitrogen-containing layer to diffuse into the high-k dielectric layer to reduce a density of active oxygen vacancies in the high-k dielectric layer. Finally, the method includes forming a gate electrode layer on the high-k dielectric layer.
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公开(公告)号：US20190279982A1
公开(公告)日：2019-09-12
申请号：US16421299
申请日：2019-05-23
Applicant: Semiconductor Manufacturing International (Beijing) Corporation , Semiconductor Manufacturing International (Shanghai) Corporation
Inventor： Fei Zhou , Zhongshan Hong
IPC: H01L27/092 , H01L29/66 , H01L21/8238 , H01L21/3105 , H01L21/321 , H01L27/02 , H01L29/10 , H01L29/08 , H01L29/06 , H01L29/49 , H01L29/78
Abstract: A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the semiconductor substrate and separated by a trench. The first fin includes a first portion having a first conductivity type and a second portion having a second conductivity type different from the first conductivity type, the first and second portions are adjacent to each other, and the second portion connected to the second fin through the semiconductor substrate. The semiconductor device also includes a gate structure on the first and second portions and including a gate insulator layer on the first and second portions, a gate on a portion of the gate insulator layer on the first portion, and a dummy gate on the second portion and including an insulating layer or an undoped semiconductor layer and adjacent to the gate.
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Patent Agency Ranking
公开(公告)号：US10128231B2
公开(公告)日：2018-11-13
申请号：US15794876
申请日：2017-10-26
Inventor： Zhongshan Hong
IPC: H01L21/02 , H01L21/461 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L49/02 , H01L29/66 , H01L29/772
Abstract: An integrated device includes a field effect transistor formed within and upon an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. The resistor includes a resistor body being an enclosure portion of the first conductive layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body. A method for manufacturing a semiconductor device includes forming a gate stacked structure and a resistor stacked structure at the same time by patterning a dielectric layer, a first conductive layer and a second conductive layer. The method also includes forming a resistor having a resistor body by patterning the resistor stacked structure.
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公开(公告)号：US09831308B2
公开(公告)日：2017-11-28
申请号：US15370721
申请日：2016-12-06
Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Inventor： Zhongshan Hong
IPC: H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/00 , H01L29/06 , H01L21/3065 , H01L21/308 , H01L21/306 , B82Y30/00
CPC classification number: H01L29/0676 , B82Y30/00 , H01L21/30625 , H01L21/3065 , H01L21/3081 , H01L21/3083 , H01L21/3086
Abstract: A semiconductor device includes a plurality of substantially vertical semiconductor pillars on a substrate, and a hard mask layer overlying the plurality of semiconductor pillars. A contiguous portion of the hard mask layer connects two or more of the plurality of semiconductor pillars.
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公开(公告)号：US08956883B1
公开(公告)日：2015-02-17
申请号：US14228410
申请日：2014-03-28
Applicant: Semiconductor Manufacturing International (Beijing) Corporation , Semiconductor Manufacturing International (Shanghai) Corporation
Inventor： Zhongshan Hong
CPC classification number: H01L43/12 , G11C11/155 , G11C11/161 , G11C11/1673 , H01L43/08
Abstract: A method is provided for fabricating a magnetic tunnel junction. The method includes providing a substrate having a first dielectric layer and a first electrode layer formed in the first dielectric layer; and forming a composite magnetic layer on the first electrode layer and the first dielectric layer. The method also includes forming a first mask layer with a first shape and a second mask layer on a surface of the composite magnetic layer. Further, the method includes removing a portion of the first mask layer to form an opening; and forming a sidewall spacer on side surfaces of the first mask layer and the second mask layer in the opening. Further, the method also includes removing the second mask layer; and forming a composite magnetic structure having the first shape outer surface and a second shape inner surface by etching the composite magnetic layer.
Abstract translation: 提供了一种用于制造磁性隧道结的方法。 该方法包括提供具有形成在第一电介质层中的第一电介质层和第一电极层的衬底; 以及在所述第一电极层和所述第一电介质层上形成复合磁性层。 该方法还包括在复合磁性层的表面上形成具有第一形状的第一掩模层和第二掩模层。 此外，该方法包括移除第一掩模层的一部分以形成开口; 以及在所述开口中的所述第一掩模层和所述第二掩模层的侧表面上形成侧壁间隔物。 此外，该方法还包括移除第二掩模层; 以及通过蚀刻复合磁性层形成具有第一形状外表面和第二形状内表面的复合磁性结构。
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公开(公告)号：US10418454B2
公开(公告)日：2019-09-17
申请号：US15973711
申请日：2018-05-08
Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
Inventor： Yong Li , Zhongshan Hong
IPC: H01L29/04 , H01L29/423 , H01L27/088 , H01L29/08 , H01L21/28 , H01L21/8234
Abstract: This disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device may include a substrate; a first fin on the substrate for forming a first electronic component; a first gate structure on a portion of the first fin including a first gate dielectric layer on a portion of the first fin and a first gate on the first gate dielectric layer; and a first source region and a first drain region that each at one of two sides of the first gate structure and at least partially located in the first fin, where the first gate dielectric layer comprises a first region abutting against the first drain region, a second region abutting against the first source region, and a third region between the first region and the second region, and wherein thickness of the first region is greater than that of the third region.
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公开(公告)号：US10340274B2
公开(公告)日：2019-07-02
申请号：US15473183
申请日：2017-03-29
Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Inventor： Fei Zhou , Zhongshan Hong
IPC: H01L29/66 , H01L27/092 , H01L29/49 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10 , H01L21/3105 , H01L21/321 , H01L21/8238 , H01L27/02 , H01L21/28
Abstract: A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the semiconductor substrate and separated by a trench. The first fin includes a first portion having a first conductivity type and a second portion having a second conductivity type different from the first conductivity type, the first and second portions are adjacent to each other, and the second portion connected to the second fin through the semiconductor substrate. The semiconductor device also includes a gate structure on the first and second portions and including a gate insulator layer on the first and second portions, a gate on a portion of the gate insulator layer on the first portion, and a dummy gate on the second portion and including an insulating layer or an undoped semiconductor layer and adjacent to the gate.
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