公开(公告)号：US20240332398A1

公开(公告)日：2024-10-03

申请号：US18191295

申请日：2023-03-28

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Roy R. Yu ,  SON NGUYEN

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5223 ,  H01L23/5286 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor structure with a nanosheet device region with GAA nanosheet FETs on a bottom dielectric isolation layer. The GAA nanosheet FETs connect by a frontside contact to the frontside back-end-of-line (BEOL) interconnect wiring and by a backside contact to the backside BEOL interconnect wiring. The semiconductor structure includes a finFET device region with one or more finFET devices on bottom interlayer dielectric material. The finFET devices with a thick gate oxide connect by a frontside contact to the frontside BEOL interconnect wiring. The semiconductor structure also includes a three-dimensional MIM capacitor region with one or more three-dimensional MIM capacitors. The three-dimensional MIM capacitors with a high capacitance have a fin-like backside metal plate covered by a high-k dielectric material or super capacitor materials that is under a frontside metal plate. The three-dimensional MIM capacitors connect to the frontside BEOL interconnect wiring and the backside BEOL interconnect wiring.

公开(公告)号：US20240332073A1

公开(公告)日：2024-10-03

申请号：US18738390

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang LIN ,  Wei-Hao WU ,  Teng-Chun TSAI

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L21/76835 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4232

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.

公开(公告)号：US12107132B2

公开(公告)日：2024-10-01

申请号：US17491408

申请日：2021-09-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Indira Seshadri ,  Eric Miller ,  Kangguo Cheng

IPC: H01L29/417 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/41775 ,  H01L21/823475 ,  H01L23/5286 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/78696

Abstract: Embodiments disclosed herein include a semiconductor structure for reducing contact to contact shorting. The semiconductor structure may include a gate cut region with a liner and a dielectric core confined within a first lateral side of the liner and a second lateral side of the liner. The semiconductor structure may also include a first source/drain (S/D) contact overlapping the first lateral side and the dielectric core. The first S/D may include a line-end that contacts the second lateral side of the liner.

公开(公告)号：US20240321872A1

公开(公告)日：2024-09-26

申请号：US18125447

申请日：2023-03-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Thomas Obrien ,  Krishna Ganesan ,  Ankit Kirit Lakhani ,  Prabhjot Kaur Luthra ,  Nidhi Khandelwal ,  Clifford J. Engel ,  Baofu Zhu ,  Meenakshisundaram Ramanathan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: Techniques to form an integrated circuit having a gate cut between adjacent pairs of semiconductor devices. At least one of those adjacent pairs of semiconductor devices includes a conductive link (e.g., a bridge) through the gate cut to connect the adjacent gates together. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. A conductive link extends over a given gate cut to electrically connect the adjacent gate electrodes together. A dielectric layer extends over the bridged gate electrodes and the conductive link, and may have different thicknesses over those respective features.

公开(公告)号：US20240321870A1

公开(公告)日：2024-09-26

申请号：US18734212

申请日：2024-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Yu LAI ,  Chih-Liang CHEN ,  Chi-Yu LU ,  Shang-Syuan CIOU ,  Hui-Zhong ZHUANG ,  Ching-Wei TSAI ,  Shang-Wen CHANG

IPC: H01L27/06 ,  G06F30/392 ,  G06F30/394 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0694 ,  G06F30/392 ,  G06F30/394 ,  H01L21/0259 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5283 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

公开(公告)号：US20240315051A1

公开(公告)日：2024-09-19

申请号：US18679002

申请日：2024-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shy-Jay Lin ,  Chien-Min Lee ,  Hiroki Noguchi ,  MingYuan Song ,  Yen-Lin Huang ,  William Joseph Gallagher

IPC: H10B61/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H10B61/22 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/528

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

公开(公告)号：US12094780B2

公开(公告)日：2024-09-17

申请号：US18223981

申请日：2023-07-19

Applicant: Intel Corporation

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  G06F30/39 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  G06F30/39 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00 ,  H01L2924/0002

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US12087861B2

公开(公告)日：2024-09-10

申请号：US17814681

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Tai-Chun Huang ,  Tien-I Bao

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/033 ,  H01L21/768 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7851 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76843 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/5283 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878

Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.

公开(公告)号：US20240282627A1

公开(公告)日：2024-08-22

申请号：US18629122

申请日：2024-04-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Peng-Soon LIM ,  Chung-Liang Cheng ,  Huang-Lin Chao

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088

CPC classification number: H01L21/76871 ,  H01L21/76804 ,  H01L21/76865 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/088 ,  H01L21/76843 ,  H01L21/823412 ,  H01L21/823456

Abstract: A semiconductor device with liner-free contact structures and a method of fabricating the same are disclosed. The method includes forming first and second source/drain (S/D) regions on first and second fin structures, forming a first dielectric layer between the first and second S/D regions, forming first and second gate-all-around (GAA) structures on the first and second fin structures, forming a second dielectric layer on the first and second GAA structures and the first dielectric layer, forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer, selectively forming a seed layer on top surfaces of the first and second GAA structures and the first dielectric layer that are exposed in the tapered trench opening, and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.

公开(公告)号：US12068200B2

公开(公告)日：2024-08-20

申请号：US18190563

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Yu Huang ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823475 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes two stacks of channel members; a source/drain feature extending between the two stacks of channel members along a direction; a source/drain contact disposed under and electrically coupled to the source/drain feature; two gate structures over and interleaved with the two stacks of channel members; a low-k spacer horizontally surrounding the source/drain contact; and a dielectric layer horizontally surrounding the low-k spacer.