公开(公告)号：US20210242334A1

公开(公告)日：2021-08-05

申请号：US17152448

申请日：2021-01-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Yun LI ,  Tsai-Yu HUANG ,  Huicheng CHANG ,  Yee-Chia YEO

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L29/10 ,  H01L29/161 ,  H01L29/78 ,  H01L21/02 ,  H01L21/225 ,  H01L21/8238

摘要： A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate and forming an isolation structure over the substrate. In addition, the fin structure is protruded from the isolation structure. The method further includes trimming the fin structure to a first width and forming a Ge-containing material covering the fin structure. The method further includes annealing the fin structure and the Ge-containing material to form a modified fin structure. The method also includes trimming the modified fin structure to a second width.

公开(公告)号：US20180197955A1

公开(公告)日：2018-07-12

申请号：US15913414

申请日：2018-03-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Chao HUANG ,  Yee-Chia YEO ,  Chao-Hsiung WANG ,  Chun-Chieh LIN ,  Chenming HU

IPC分类号： H01L29/10 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

公开(公告)号：US20170271449A1

公开(公告)日：2017-09-21

申请号：US15613778

申请日：2017-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Chao Huang ,  Yee-Chia YEO ,  Chao-Hsiung WANG ,  Chun-Chieh LIN ,  Chenming HU

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/1054 ,  H01L21/02142 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834

摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

公开(公告)号：US20240145569A1

公开(公告)日：2024-05-02

申请号：US18404299

申请日：2024-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yee-Chia YEO ,  Sung-Li WANG ,  Chi On CHUI ,  Jyh-Cherng SHEU ,  Hung-Li CHIANG ,  I-Sheng CHEN

IPC分类号： H01L29/45 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/5226 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/7851 ,  H01L21/823807 ,  H01L29/456 ,  H01L2029/7858

摘要： A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US20240088267A1

公开(公告)日：2024-03-14

申请号：US18518131

申请日：2023-11-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Yi PENG ,  Chih Chieh YEH ,  Chih-Sheng CHANG ,  Hung-Li CHIANG ,  Hung-Ming CHEN ,  Yee-Chia YEO

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/785 ,  H01L29/6681

摘要： A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

公开(公告)号：US20230395701A1

公开(公告)日：2023-12-07

申请号：US17832306

申请日：2022-06-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Ming CHEN ,  Szu-Ying CHEN ,  Yen-Chun HUANG ,  Sen-Hong SYUE ,  Huicheng CHANG ,  Yee-Chia YEO

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66795 ,  H01L29/7812 ,  H01L29/7869

摘要： A method of manufacturing a semiconductor device includes forming a dummy gate structure over a substrate. The dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode layer. Sidewall spacers including one or more layers of insulating materials are formed on sidewalls of the dummy gate structure. A silicon based liner is formed over the sidewall spacers. A first insulating layer is formed over the silicon based liner. The silicon based liner and the first insulating layer are thermally treating causing a reduction in a volume of the first insulating layer and an increase in a volume of the silicon based liner. The dummy gate structure is removed to form a gate space in the first insulating layer. The gate space is formed with a high-k dielectric layer and a first conductive layer.

公开(公告)号：US20230299175A1

公开(公告)日：2023-09-21

申请号：US17696257

申请日：2022-03-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Rui CHEN ,  Yi-Fan CHEN ,  Szu-Ying CHEN ,  Sen-Hong SYUE ,  Huicheng CHANG ,  Yee-Chia YEO

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/49 ,  H01L29/40

CPC分类号： H01L29/66545 ,  H01L21/02211 ,  H01L21/02323 ,  H01L21/02343 ,  H01L29/4983 ,  H01L29/401 ,  H01L21/0214 ,  H01L21/0228 ,  H01L21/02337 ,  H01L29/66795

摘要： A method of forming a semiconductor device includes forming a sacrificial gate structure over a substrate, depositing a spacer layer on the sacrificial gate structure in a conformal manner, performing a multi-step oxidation process to the spacer layer, etching the spacer layer to form gate sidewall spacers on opposite sidewalls of the sacrificial gate structure, removing the sacrificial gate structure to form a trench between the gate sidewalls spacers, and forming a metal gate structure in the trench.

公开(公告)号：US20230068951A1

公开(公告)日：2023-03-02

申请号：US17461338

申请日：2021-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Kai HSIAO ,  Tsai-Yu HUANG ,  Hui-Cheng CHANG ,  Yee-Chia YEO

IPC分类号： H01L21/762 ,  H01L29/66

摘要： A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.

公开(公告)号：US20220028974A1

公开(公告)日：2022-01-27

申请号：US17498593

申请日：2021-10-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Yi PENG ,  Chih Chieh YEH ,  Chih-Sheng CHANG ,  Hung-Li CHIANG ,  Hung-Ming CHEN ,  Yee-Chia YEO

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L29/417 ,  H01L29/267 ,  H01L29/66

摘要： A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

公开(公告)号：US20210313438A1

公开(公告)日：2021-10-07

申请号：US17353460

申请日：2021-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yee-Chia YEO ,  Sung-Li WANG ,  Chi On CHUI ,  Jyh-Cherng SHEU ,  Hung-Li CHIANG ,  I-Sheng CHEN

IPC分类号： H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

摘要： A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.