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公开(公告)号：US20240113221A1
公开(公告)日：2024-04-04
申请号：US18521913
申请日：2023-11-28
Inventor： Chun-Hsiung TSAI , Shahaji B. MORE , Cheng-Yi PENG , Yu-Ming LIN , Kuo-Feng YU , Ziwei FANG
IPC: H01L29/78 , H01L21/02 , H01L21/265 , H01L21/3065 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/08 , H01L29/165 , H01L29/167 , H01L29/45 , H01L29/66
CPC classification number: H01L29/7848 , H01L21/02532 , H01L21/26513 , H01L21/3065 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L29/0649 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/45 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/66795 , H01L29/785 , H01L29/7851 , H01L21/0274
Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.
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公开(公告)号：US20240243184A1
公开(公告)日：2024-07-18
申请号：US18434577
申请日：2024-02-06
Inventor： Cheng-Yi PENG , Ching-Hua LEE , Song-Bor LEE
IPC: H01L29/66 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/786
CPC classification number: H01L29/66439 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/775 , H01L29/78696
Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions
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3.发明公开
公开(公告)号：US20240194760A1
公开(公告)日：2024-06-13
申请号：US18308026
申请日：2023-04-27
Inventor： Chih-Hao CHANG , Cheng-Yi PENG , Wei-Yang LEE , Chia-Pin LIN
IPC: H01L29/49 , H01L21/28 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775
CPC classification number: H01L29/4991 , H01L21/28123 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66553 , H01L29/775
Abstract: Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device includes a gate-all-around transistor having one or more dielectric regions that include or more dielectric gases. The dielectric regions may include a first dielectric region between epitaxial regions (e.g., source/drain regions) and a first portion of a gate structure of the gate-all-around transistor. The dielectric regions may further include a second dielectric region between a contact structure of gate-all-around transistor and a second portion of the gate structure. By including the dielectric regions in the gate-all-around transistor, a parasitic capacitance associated with the gate-all-around transistor may be reduced relative to another gate-all-around transistor not including the dielectric regions.
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公开(公告)号：US20240088267A1
公开(公告)日：2024-03-14
申请号：US18518131
申请日：2023-11-22
Inventor： Cheng-Yi PENG , Chih Chieh YEH , Chih-Sheng CHANG , Hung-Li CHIANG , Hung-Ming CHEN , Yee-Chia YEO
IPC: H01L29/66 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/78
CPC classification number: H01L29/66795 , H01L29/0649 , H01L29/41725 , H01L29/41791 , H01L29/42356 , H01L29/785 , H01L29/6681
Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
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公开(公告)号：US20230307522A1
公开(公告)日：2023-09-28
申请号：US18130296
申请日：2023-04-03
Inventor： Cheng-Yi PENG , Wen-Yuan CHEN , Wen-Hsing HSIEH , Yi-Ju HSU , Jon-Hsu HO , Song-Bor LEE , Bor-Zen TIEN
IPC: H01L29/66 , H01L21/02 , H01L27/088 , H01L21/8234
CPC classification number: H01L29/66545 , H01L21/0214 , H01L21/02164 , H01L21/02203 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L27/0886
Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.
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公开(公告)号：US20220028974A1
公开(公告)日：2022-01-27
申请号：US17498593
申请日：2021-10-11
Inventor： Cheng-Yi PENG , Chih Chieh YEH , Chih-Sheng CHANG , Hung-Li CHIANG , Hung-Ming CHEN , Yee-Chia YEO
IPC: H01L29/08 , H01L29/78 , H01L29/417 , H01L29/267 , H01L29/66
Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
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公开(公告)号：US20230154998A1
公开(公告)日：2023-05-18
申请号：US18100302
申请日：2023-01-23
Inventor： Chun-Chieh LU , Carlos H. DIAZ , Chih-Sheng CHANG , Cheng-Yi PENG , Ling-Yen YEH
CPC classification number: H01L29/516 , H01L29/78391 , H01L29/517 , H01L21/324 , H01L21/02181 , H01L28/40 , H01L21/02304 , H01L21/0228 , H01L29/785 , H01L21/02356 , H01L21/02189 , H01L29/6684 , H01L29/40111 , H01L21/02194 , H01L29/66545
Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
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公开(公告)号：US20220172998A1
公开(公告)日：2022-06-02
申请号：US17671405
申请日：2022-02-14
Inventor： Yasutoshi OKUNO , Cheng-Yi PENG , Ziwei FANG , I-Ming CHANG , Akira MINEJI , Yu-Ming LIN , Meng-Hsuan HSIAO
IPC: H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/203 , H01L27/092 , H01L21/8238
Abstract: A method of forming a semiconductor device comprises forming a fin structure; forming a source/drain structure in the fin structure; and forming a gate electrode over the fin structure. The source/drain structure includes Si−x−yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, 0.01≤x≤0.1, and 0.01≤y≤0.
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公开(公告)号：US20210359085A1
公开(公告)日：2021-11-18
申请号：US17385031
申请日：2021-07-26
Inventor： Cheng-Yi PENG , Ting TSAI , Chung-Wei HUNG , Jung-Ting CHEN , Ying-Hua LAI , Song-Bor LEE , Bor-Zen TIEN
Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.
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公开(公告)号：US20210351282A1
公开(公告)日：2021-11-11
申请号：US17379551
申请日：2021-07-19
Inventor： Cheng-Yi PENG , Wen-Yuan CHEN , Wen-Hsing HSIEH , Yi-Ju HSU , Jon-Hsu HO , Song-Bor LEE , Bor-Zen TIEN
IPC: H01L29/66 , H01L21/8234 , H01L27/088 , H01L21/02
Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.
