公开(公告)号：US20160087106A1

公开(公告)日：2016-03-24

申请号：US14489902

申请日：2014-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Tsu-Hui Su ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L29/788 ,  H01L29/40 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L29/7883 ,  G11C16/0483 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a structure and method for forming a flash memory cell with an improved erase speed and erase current. Si dots are used for charge trapping and an ONO sandwich structure is formed over the Si dots. Erase operation includes direct tunneling as well as FN tunneling which helps increase erase speed without compensating data retention.

Abstract translation: 本发明涉及用于形成具有改进的擦除速度和擦除电流的闪存单元的结构和方法。 Si点用于电荷俘获，并且在Si点上形成ONO夹层结构。 擦除操作包括直接隧道和FN隧道，这有助于提高擦除速度，而不会补偿数据保留。

公开(公告)号：US20150371994A1

公开(公告)日：2015-12-24

申请号：US14308808

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a first tunnel oxide is formed over a semiconductor substrate. A self-assembled monolayer (SAM) is then formed on the first tunnel oxide. The SAM includes spherical or spherical-like crystalline silicon dots having respective diameters which are less than approximately 30 nm. A second tunnel oxide is then formed over the SAM.

Abstract translation: 本公开的一些实施例涉及用于形成快闪存储器的方法。 在该方法中，在半导体衬底上形成第一隧道氧化物。 然后在第一隧道氧化物上形成自组装单层（SAM）。 SAM包括具有小于约30nm的相应直径的球形或球形晶体硅点。 然后在SAM上形成第二隧道氧化物。

公开(公告)号：US09184041B2

公开(公告)日：2015-11-10

申请号：US13925940

申请日：2013-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L21/02 ,  H01L21/822

CPC classification number: H01L23/562 ,  H01L21/02016 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3205 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L21/8221 ,  H01L22/20 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/10829 ,  H01L27/10861 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.

Abstract translation: 由深沟槽电容器引起的晶片弯曲由晶片背面形成的结构改善。 反面的结构包括拉伸膜。 膜可以形成在晶片背面的沟槽内，这增强了它们的作用。 在一些实施例中，晶片用于形成3D-IC器件。 在一些实施例中，3D-IC器件包括高电压或高功率电路。

公开(公告)号：US11532642B2

公开(公告)日：2022-12-20

申请号：US17189709

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Eugene I-Chun Chen ,  Kuan-Liang Liu ,  Szu-Yu Wang ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Chih-Ping Chao ,  Alexander Kalnitsky

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/02

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

公开(公告)号：US10777649B2

公开(公告)日：2020-09-15

申请号：US15463692

申请日：2017-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chih-Ming Chen ,  Chia-Shiung Tsai ,  Chung-Yi Yu ,  Szu-Yu Wang

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L29/788 ,  H01L21/3205 ,  H01L21/321 ,  H01L29/49

Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.

公开(公告)号：US09929007B2

公开(公告)日：2018-03-27

申请号：US14583291

申请日：2014-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Tsu-Hui Su ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L29/792 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L21/02247 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

Abstract: The present disclosure relates to a structure and method for reducing dangling bonds around quantum dots in a memory cell. In some embodiments, the structure has a semiconductor substrate having a tunnel dielectric layer disposed over it and a plurality of quantum dots disposed over the tunnel dielectric layer. A passivation layer is formed conformally over outer surfaces of the quantum dots and a top dielectric layer is disposed conformally around the passivation layer. The passivation layer can be formed prior to forming the top dielectric layer over the quantum dots or after forming the top dielectric layer. The passivation layer reduces the dangling bonds at an interface between the quantum dots and the top dielectric layer, thereby preventing trap sites that may hinder operations of the memory cell.

公开(公告)号：US20170194445A1

公开(公告)日：2017-07-06

申请号：US15463692

申请日：2017-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chih-Ming Chen ,  Chia-Shiung Tsai ,  Chung-Yi Yu ,  Szu-Yu Wang

IPC: H01L29/423 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/28 ,  H01L29/66

Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.

公开(公告)号：US20150287737A1

公开(公告)日：2015-10-08

申请号：US14745568

申请日：2015-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Tsung-Yu Chen ,  Cheng-Te Lee ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/423 ,  H01L29/792 ,  H01L29/06

CPC classification number: H01L27/11568 ,  H01L21/02118 ,  H01L21/28273 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/32055 ,  H01L21/32139 ,  H01L21/8239 ,  H01L27/11521 ,  H01L27/11565 ,  H01L29/0665 ,  H01L29/0692 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/792 ,  Y10S977/774

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements within a memory cell. A copolymer solution having first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material having a regular pattern of micro-domains of the second polymer species within a polymer matrix having the first polymer species. The second polymer species is then removed resulting with a pattern of holes within the polymer matrix. An etch is then performed through the holes utilizing the polymer matrix as a hard-mask to form a substantially identical pattern of holes in a dielectric layer disposed over a seed layer disposed over the substrate surface. Epitaxial deposition onto the seed layer then utilized to grow a substantially uniform pattern of discrete storage elements within the dielectric layer.

Abstract translation: 本公开的一些实施例涉及实现存储器单元内的离散存储元件的基本上均匀的图案的方法。 将具有第一和第二聚合物种类的共聚物溶液旋涂在基材的表面上，并在具有第二聚合物物质的聚合物基质的具有规则形式的第二聚合物物质的相分离材料中进行自组装， 第一种聚合物种类。 然后除去聚合物基质中的第二种聚合物物质，形成孔。 然后通过孔进行蚀刻，利用聚合物基质作为硬掩模，以在设置在衬底表面上的种子层上的电介质层中形成基本上相同的孔的图案。 然后将种子层上的外延沉积物用于在介电层内生长基本上均匀的离散存储元件图案。

公开(公告)号：US09064821B2

公开(公告)日：2015-06-23

申请号：US13974137

申请日：2013-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Tsung-Yu Chen ,  Cheng-Te Lee ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L21/32 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8239 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/02

CPC classification number: H01L27/11568 ,  H01L21/02118 ,  H01L21/28273 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/32055 ,  H01L21/32139 ,  H01L21/8239 ,  H01L27/11521 ,  H01L27/11565 ,  H01L29/0665 ,  H01L29/0692 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/792 ,  Y10S977/774

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements within a memory cell. A copolymer solution comprising first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material comprising a regular pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The second polymer species is then removed resulting with a pattern of holes within the polymer matrix. An etch is then performed through the holes utilizing the polymer matrix as a hard-mask to form a substantially identical pattern of holes in a dielectric layer disposed over a seed layer disposed over the substrate surface. Epitaxial deposition onto the seed layer then utilized to grow a substantially uniform pattern of discrete storage elements within the dielectric layer.

Abstract translation: 本公开的一些实施例涉及实现存储器单元内的离散存储元件的基本上均匀的图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在基材的表面上，并进行自组装成相分离的材料，该相分离材料包含第二聚合物物质的规则形式的第二聚合物种类的聚合物基质， 第一种聚合物种类。 然后除去聚合物基质中的第二种聚合物物质，形成孔。 然后通过孔进行蚀刻，利用聚合物基质作为硬掩模，以在设置在衬底表面上的种子层上的电介质层中形成基本上相同的孔的图案。 然后将种子层上的外延沉积物用于在介电层内生长基本上均匀的离散存储元件图案。

公开(公告)号：US20150054059A1

公开(公告)日：2015-02-26

申请号：US13974155

申请日：2013-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Cheng-Te Lee ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L21/28273 ,  H01L21/31155 ,  H01L21/32105 ,  H01L21/32139 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements comprising a substantially equal size within a memory cell. A copolymer solution comprising first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material comprising a regular pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first or second polymer species is then removed resulting with a pattern of micro-domains or the polymer matrix with a pattern of holes, which may be utilized as a hard-mask to form a substantially identical pattern of discrete storage elements through an etch, ion implant technique, or a combination thereof.

Abstract translation: 本公开的一些实施例涉及一种实现在存储器单元内包括基本上相等尺寸的离散存储元件的基本上均匀的图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在基材的表面上，并进行自组装成相分离的材料，该相分离材料包含第二聚合物物质的规则形式的第二聚合物种类的聚合物基质， 第一种聚合物种类。 然后去除第一或第二聚合物物质，其具有微畴图案或具有空穴图案的聚合物基质，其可以用作硬掩模，以通过蚀刻形成基本相同的离散存储元件图案， 离子注入技术或其组合。