Invention Grant
US09184041B2 Integrated circuit with backside structures to reduce substrate warp
有权
具有背面结构的集成电路，以减少基板翘曲
- Patent Title: Integrated circuit with backside structures to reduce substrate warp
- Patent Title (中): 具有背面结构的集成电路，以减少基板翘曲
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Application No.: US13925940Application Date: 2013-06-25
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Publication No.: US09184041B2Publication Date: 2015-11-10
- Inventor: Chih-Ming Chen , Szu-Yu Wang , Chung-Yi Yu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/822
Abstract:
Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.
Public/Granted literature
- US20140374879A1 INTEGRATED CIRCUIT WITH BACKSIDE STRUCTURES TO REDUCE SUBSTRATE WRAP Public/Granted day:2014-12-25
Information query
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