公开(公告)号：US10998494B2

公开(公告)日：2021-05-04

申请号：US16587499

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Chern-Yow Hsu ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

公开(公告)号：US20170243836A1

公开(公告)日：2017-08-24

申请号：US15589195

申请日：2017-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L23/00 ,  H01L21/3205 ,  H01L25/00 ,  H01L21/78 ,  H01L49/02 ,  H01L21/306 ,  H01L21/02 ,  H01L21/768 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/02016 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3205 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L21/8221 ,  H01L22/20 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/10829 ,  H01L27/10861 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.

公开(公告)号：US09634105B2

公开(公告)日：2017-04-25

申请号：US14596487

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chih-Ming Chen ,  Chia-Shiung Tsai ,  Chung-Yi Yu ,  Szu-Yu Wang

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L21/32055 ,  H01L21/321 ,  H01L29/42328 ,  H01L29/42348 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.

公开(公告)号：US20190244914A1

公开(公告)日：2019-08-08

申请号：US16386630

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/78 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L27/108 ,  H01L49/02 ,  H01L21/02 ,  H01L21/302 ,  H01L21/306

CPC classification number: H01L23/562 ,  H01L21/02016 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3205 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L21/8221 ,  H01L22/20 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/10829 ,  H01L27/10861 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some embodiments relate to a method. In this method, a semiconductor wafer having a frontside and a backside is received. A frontside structure is formed on the frontside of the semiconductor wafer. The frontside structure exerts a first wafer-bowing stress that bows the semiconductor wafer by a first bow amount. A characteristic is determined for one or more stress-inducing films to be formed based on the first bow amount. The one or more stress-inducing films are formed with the determined characteristic on the backside of the semiconductor wafer and/or on the frontside of the semiconductor wafer to reduce the first bow amount in the semiconductor wafer.

公开(公告)号：US10276513B2

公开(公告)日：2019-04-30

申请号：US15589195

申请日：2017-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L23/00 ,  H01L21/02 ,  H01L27/108 ,  H01L49/02 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L21/822

Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.

公开(公告)号：US09209190B2

公开(公告)日：2015-12-08

申请号：US13925984

申请日：2013-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/08

CPC classification number: H01L27/10829 ,  H01L24/73 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/91 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present disclosure relates to a method of forming a capacitor structure, including depositing a plurality of first polysilicon (POLY) layers of uniform thickness separated by a plurality of oxide/nitride/oxide (ONO) layers over a bottom and sidewalls of a recess and substrate surface. A second POLY layer is deposited over the plurality of first POLY layers, is separated by an ONO layer, and fills a remainder of the recess. Portions of the second POLY layer and the second ONO layer are removed with a first chemical-mechanical polish (CMP). A portion of each of the plurality of first POLY layers and the first ONO layers on the surface which are not within a doped region of the capacitor structure are removed with a first pattern and etch process such that a top surface of each of the plurality of first POLY layers is exposed for contact formation.

Abstract translation: 本公开涉及一种形成电容器结构的方法，包括在凹槽的底部和侧壁上沉积由多个氧化物/氮化物/氧化物（ONO）层隔开的多个均匀厚度的多个第一多晶硅（POLY）层，以及 基材表面。 第二POLY层沉积在多个第一POLY层上，被ONO层隔开，并填充凹槽的其余部分。 用第一化学机械抛光（CMP）去除第二POLY层和第二ONO层的部分。 多个第一POLY层和表面上不在电容器结构的掺杂区域内的第一ONO层的一部分用第一图案和蚀刻工艺去除，使得多个第一POLY层中的每一个的顶表面 第一POLY层被暴露以形成接触。

公开(公告)号：US20150069541A1

公开(公告)日：2015-03-12

申请号：US14023552

申请日：2013-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Chern-Yow Hsu ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract translation: 本公开的一些实施例涉及一种实现具有低于某些光刻技术的较低分辨率极限的最小尺寸的磁性随机存取存储器（MRAM）单元的基本均匀图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在位于基材表面上的异质结构上。 异质结构包括由绝缘层分开的第一和第二铁磁层。 将共聚物溶液自组装成包含第二聚合物种类的微畴图案的相分离材料在包含第一聚合物种类的聚合物基质内。 然后除去第一聚合物物质，留下第二聚合物物质的微畴图案。 通过在利用微畴图案作为硬掩模的同时蚀刻异质结构来形成异质结构内的磁记忆单元的图案。

公开(公告)号：US20220189997A1

公开(公告)日：2022-06-16

申请号：US17189709

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Eugene I-Chun Chen ,  Kuan-Liang Liu ,  Szu-Yu Wang ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Chih-Ping Chao ,  Alexander Kalnitsky

IPC: H01L27/12 ,  H01L21/762

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

公开(公告)号：US10833026B2

公开(公告)日：2020-11-10

申请号：US16386630

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L23/00 ,  H01L21/02 ,  H01L27/108 ,  H01L21/302 ,  H01L49/02 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L21/822

Abstract: Some embodiments relate to a method. In this method, a semiconductor wafer having a frontside and a backside is received. A frontside structure is formed on the frontside of the semiconductor wafer. The frontside structure exerts a first wafer-bowing stress that bows the semiconductor wafer by a first bow amount. A characteristic is determined for one or more stress-inducing films to be formed based on the first bow amount. The one or more stress-inducing films are formed with the determined characteristic on the backside of the semiconductor wafer and/or on the frontside of the semiconductor wafer to reduce the first bow amount in the semiconductor wafer.

公开(公告)号：US20160204212A1

公开(公告)日：2016-07-14

申请号：US14596487

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chih-Ming Chen ,  Chia-Shiung Tsai ,  Chung-Yi Yu ,  Szu-Yu Wang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L21/32055 ,  H01L21/321 ,  H01L29/42328 ,  H01L29/42348 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.

Abstract translation: 提供了用于闪存单元的量子纳米尖端（QNT）薄膜，例如硅纳米尖端（SiNT）薄膜以增加擦除速度。 QNT薄膜包括布置在第一介电层上的第一电介质层和第二电介质层。 此外，QNT薄膜包括布置在第一介电层上并延伸到第二介电层中的QNT。 QNT的高度与宽度之比大于50％。 还提供了基于QNT的闪存单元和用于制造基于SiNT的快闪存储单元的方法。