公开(公告)号：US20220189997A1

公开(公告)日：2022-06-16

申请号：US17189709

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Eugene I-Chun Chen ,  Kuan-Liang Liu ,  Szu-Yu Wang ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Chih-Ping Chao ,  Alexander Kalnitsky

IPC: H01L27/12 ,  H01L21/762

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

公开(公告)号：US11264378B2

公开(公告)日：2022-03-01

申请号：US16724024

申请日：2019-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Yu Chen ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L49/02 ,  H01L23/522

Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

公开(公告)号：US10515949B2

公开(公告)日：2019-12-24

申请号：US14056725

申请日：2013-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Yu Chen ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L49/02

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

公开(公告)号：US20170110420A1

公开(公告)日：2017-04-20

申请号：US15051197

申请日：2016-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Chih-Ping Chao ,  Kuan-Chi Tsai ,  Shih-Shiung Chen ,  Wei-Kung Tsai

IPC: H01L23/66 ,  H01L29/10 ,  H01L23/48 ,  H01L23/31 ,  H01L27/12 ,  H01L21/683 ,  H01L23/00 ,  H01L21/28 ,  H01L21/84 ,  H01L21/762 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/66 ,  H01L21/28008 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L27/1211 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1266 ,  H01L29/1079 ,  H01L2221/68368 ,  H01L2224/05025

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

公开(公告)号：US20150108607A1

公开(公告)日：2015-04-23

申请号：US14056725

申请日：2013-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Yu CHEN ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L23/538 ,  H01L49/02

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract translation: 一种集成电路包括堆叠的MIM电容器和薄膜电阻器及其制造方法。 堆叠的MIM电容器的一个电容器中的电容器底部金属和薄膜电阻器基本上处于集成电路的相同层，并且电容器底部金属和薄膜电阻器也由基本上相同的材料制成。 具有层叠MIM电容器和薄膜电阻器的集成电路可以相应地以成本有益的方式制造，以克服上述缺点。

公开(公告)号：US20200058608A1

公开(公告)日：2020-02-20

申请号：US16662391

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Chih-Ping Chao ,  Kuan-Chi Tsai ,  Shih-Shiung Chen ,  Wei-Kung Tsai

IPC: H01L23/66 ,  H01L27/12 ,  H01L23/528 ,  H01L23/48 ,  H01L21/84 ,  H01L21/768 ,  H01L21/683 ,  H01L23/522

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

公开(公告)号：US11121100B2

公开(公告)日：2021-09-14

申请号：US16662391

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Chih-Ping Chao ,  Kuan-Chi Tsai ,  Shih-Shiung Chen ,  Wei-Kung Tsai

IPC: H01L23/66 ,  H01L23/522 ,  H01L21/768 ,  H01L27/12 ,  H01L21/683 ,  H01L21/84 ,  H01L23/48 ,  H01L23/528 ,  H01L23/552

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

公开(公告)号：US10090327B2

公开(公告)日：2018-10-02

申请号：US14158430

申请日：2014-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Keng-Yu Chen ,  Wei-Kung Tsai ,  Kuan-Chi Tsai ,  Tsung-Yu Yang ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao

IPC: H01L27/12 ,  H01L27/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/28 ,  H01L23/66 ,  H01L21/762 ,  H01L21/02 ,  H01L49/02 ,  H01L21/84 ,  H01L21/763 ,  H01L23/522

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.

公开(公告)号：US20180012850A1

公开(公告)日：2018-01-11

申请号：US15696532

申请日：2017-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Chih-Ping Chao ,  Kuan-Chi Tsai ,  Shih-Shiung Chen ,  Wei-Kung Tsai

IPC: H01L23/66 ,  H01L21/683 ,  H01L21/762 ,  H01L21/768 ,  H01L29/10 ,  H01L23/00 ,  H01L23/528 ,  H01L21/28 ,  H01L23/48 ,  H01L23/31 ,  H01L21/84 ,  H01L23/522 ,  H01L27/12 ,  H01L23/552

CPC classification number: H01L23/66 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/552 ,  H01L27/1211 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2224/05025

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

公开(公告)号：US09761546B2

公开(公告)日：2017-09-12

申请号：US15051197

申请日：2016-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Chih-Ping Chao ,  Kuan-Chi Tsai ,  Shih-Shiung Chen ,  Wei-Kung Tsai

IPC: H01L23/66 ,  H01L23/528 ,  H01L29/10 ,  H01L23/48 ,  H01L23/31 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00 ,  H01L21/28 ,  H01L21/84 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L23/66 ,  H01L21/28008 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L27/1211 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1266 ,  H01L29/1079 ,  H01L2221/68368 ,  H01L2224/05025

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.