公开(公告)号：US20200286981A1

公开(公告)日：2020-09-10

申请号：US16879913

申请日：2020-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC: H01L49/02 ,  H01L23/00 ,  H01F27/28 ,  H01F27/24 ,  H01F27/29 ,  H05K1/18 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

公开(公告)号：US20200066831A1

公开(公告)日：2020-02-27

申请号：US16587305

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC: H01L49/02 ,  H01L23/522 ,  H01F27/28 ,  H01L23/00 ,  H01F27/29 ,  H01F27/24 ,  H01L21/768 ,  H05K1/18 ,  H01L23/528

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

公开(公告)号：US10672860B2

公开(公告)日：2020-06-02

申请号：US16587305

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC: H01L49/02 ,  H01F27/28 ,  H01L23/00 ,  H01F27/29 ,  H01F27/24 ,  H01L21/768 ,  H05K1/18 ,  H01L23/528 ,  H01L23/522 ,  H01L21/321 ,  H01L21/027

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

公开(公告)号：US11264378B2

公开(公告)日：2022-03-01

申请号：US16724024

申请日：2019-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Yu Chen ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L49/02 ,  H01L23/522

Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

公开(公告)号：US10515949B2

公开(公告)日：2019-12-24

申请号：US14056725

申请日：2013-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Yu Chen ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L49/02

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

公开(公告)号：US10475877B1

公开(公告)日：2019-11-12

申请号：US16106525

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC: H01L49/02 ,  H01L23/00 ,  H01F27/28 ,  H01F27/24 ,  H01F27/29 ,  H05K1/18 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/321 ,  H01L21/027

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

公开(公告)号：US20150108607A1

公开(公告)日：2015-04-23

申请号：US14056725

申请日：2013-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Yu CHEN ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L23/538 ,  H01L49/02

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract translation: 一种集成电路包括堆叠的MIM电容器和薄膜电阻器及其制造方法。 堆叠的MIM电容器的一个电容器中的电容器底部金属和薄膜电阻器基本上处于集成电路的相同层，并且电容器底部金属和薄膜电阻器也由基本上相同的材料制成。 具有层叠MIM电容器和薄膜电阻器的集成电路可以相应地以成本有益的方式制造，以克服上述缺点。