公开(公告)号：US20190066815A1

公开(公告)日：2019-02-28

申请号：US15879455

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsu Chiu ,  Shih-Feng Huang ,  Yi-Sin Wang ,  Arjit Ashok

IPC: G11C29/14 ,  G11C29/00 ,  G11C29/02 ,  G11C29/38 ,  G11C29/50 ,  G01R31/26 ,  G01R31/27

Abstract: The disclosure is related a method for testing and measuring the performances of electrical components on a semiconductor IC device through a test apparatus (also referred to as a testline) disposed in a scribe line between the semiconductor IC devices on a wafer. The test apparatus may include a built-in self-test (BIST) circuit and a duplication of the electrical components subjected to the performance measurement. Minimum and maximum testing voltages are provided to the test apparatus, where the range of voltage between the minimum and maximum testing voltages are divided into a plurality of testing operational voltages which are applied to the test apparatus. For each testing operational voltages, a memory array operation test is performed, where at least one of the testing operational voltages resulting in a performance failure is identified as the minimal operating voltage of the memory array.

公开(公告)号：US12057504B2

公开(公告)日：2024-08-06

申请号：US17751618

申请日：2022-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Sin Wang ,  Shan-Yun Cheng ,  Ching-Hung Kao ,  Jing-Jyu Chou ,  Yi-Ting Chen

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/267 ,  H01L29/66545

Abstract: A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.

公开(公告)号：US11342455B2

公开(公告)日：2022-05-24

申请号：US16821690

申请日：2020-03-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Sin Wang ,  Shan-Yun Cheng ,  Ching-Hung Kao ,  Jing-Jyu Chou ,  Yi-Ting Chen

IPC: H01L29/165 ,  H01L29/161 ,  H01L29/06 ,  H01L29/78 ,  H01L29/267 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762

Abstract: A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.

公开(公告)号：US11264378B2

公开(公告)日：2022-03-01

申请号：US16724024

申请日：2019-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Yu Chen ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L49/02 ,  H01L23/522

Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

公开(公告)号：US10515949B2

公开(公告)日：2019-12-24

申请号：US14056725

申请日：2013-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Yu Chen ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L49/02

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

公开(公告)号：US10319456B2

公开(公告)日：2019-06-11

申请号：US15879455

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsu Chiu ,  Shih-Feng Huang ,  Yi-Sin Wang ,  Arjit Ashok

IPC: G11C7/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/02 ,  G01R31/27 ,  G11C29/50 ,  G01R31/26 ,  G11C29/38

Abstract: The disclosure is related a method for testing and measuring the performances of electrical components on a semiconductor IC device through a test apparatus (also referred to as a testline) disposed in a scribe line between the semiconductor IC devices on a wafer. The test apparatus may include a built-in self-test (BIST) circuit and a duplication of the electrical components subjected to the performance measurement. Minimum and maximum testing voltages are provided to the test apparatus, where the range of voltage between the minimum and maximum testing voltages are divided into a plurality of testing operational voltages which are applied to the test apparatus. For each testing operational voltages, a memory array operation test is performed, where at least one of the testing operational voltages resulting in a performance failure is identified as the minimal operating voltage of the memory array.

公开(公告)号：US20150108607A1

公开(公告)日：2015-04-23

申请号：US14056725

申请日：2013-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Yu CHEN ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Chung-Long Chang ,  Kuan-Chi Tsai ,  Wei-Kung Tsai ,  Hsiang-Chi Chen ,  Ching-Chung Hsu ,  Cheng-Chang Hsu ,  Yi-Sin Wang

IPC: H01L27/07 ,  H01L23/538 ,  H01L49/02

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract translation: 一种集成电路包括堆叠的MIM电容器和薄膜电阻器及其制造方法。 堆叠的MIM电容器的一个电容器中的电容器底部金属和薄膜电阻器基本上处于集成电路的相同层，并且电容器底部金属和薄膜电阻器也由基本上相同的材料制成。 具有层叠MIM电容器和薄膜电阻器的集成电路可以相应地以成本有益的方式制造，以克服上述缺点。